Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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2 resultados
Resultados da Pesquisa
- Analysis of the Gate-Induced Drain Leakage of SOI Nanowire and Nanosheet MOS Transistors at High Temperatures(2022-07-04) Michelly De Souza; CERDEIRA, A.; ESTRADA, M.; BARRAUD, S.; CASSE, M.; VINET, M.; FAYNOT, O.; Marcelo Antonio Pavanello© 2022 IEEE.This work presents a comparison between the Gate-Induced Drain Leakage (GIDL) current of the nanowire (tri-gate MOSFET with narrow fin width) and nanosheet (tri-gate MOSFET with wide fin width) SOI MOSFETs at high temperatures, in the range between 300 K and 580 K. The study is conducted using experimental data, corroborated with 3D TCAD simulations. It is demonstrated that the GIDL current normalized by the total fin width is larger in nanosheet MOSFET than for the nanowire at high temperatures. Additionally, the nanosheet device presents a larger variation of the normalized GIDL current with the temperature than the nanowire one.
- Modeling of silicon stacked nanowire and nanosheet transistors at high temperatures(2022-07-04) CERDEIRA, A.; ESTRADA, M.; DA SILVA, G. M.; RODRIGUES, J. C.; Marcelo Antonio Pavanello© 2022 IEEE.In this work, we demonstrate that the Symmetric Doped Double-Gate Model (SDDGM), previously validated for modeling FinFETs, stacked nanowire, and nanosheet transistors at room temperature, can be extended for modeling stacked nanowire and nanosheet transistors at high temperatures. The modeled results are validated by comparison with experimental data.