Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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18 resultados
Resultados da Pesquisa
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- Using the Hexagonal Layout Style for MOSFETs to boost the Device Matching in Ionizing Radiation Environments(2020-08-10) PERUZZI , VINICIUS VONO; CRUZ, WILLIAM; SILVA, GABRIEL AUGUSTO DA; SIMOEN, EDDY; CLAEYS, COR; Salvador GimenezThis paper describes an experimental comparative study of the mismatching between the Diamond (hexagonal gate geometry) and Conventional (rectangular gate shape) n-chan-nel Metal-Oxide-Semiconductor (MOS) Field Effect Transis-tors (MOSFETs), which were manufactured in an 130 nm Sili-con-Germanium Bulk Complementary MOS (CMOS) technol-ogy and exposed to different X-rays Total Ionizing Doses (TIDs). The results indicate that the Diamond layout style with an alpha () angle equal to 90 ̊ for MOSFETs is capable of re-ducing the device mismatching by at least 17% regarding the electrical parameters studied as compared to the Conventional MOSFET (CnM) counterparts. Therefore, the Diamond layout style can be considered an alternative hardness-by-design (HBD) layout strategy to boost the electrical performance and TID tolerance of MOSFETs.
- Zero Temperature Coefficient behavior for Ellipsoidal MOSFET(2020) CAMILLO, L. M.; LIMA, M. P. B.; PEIXOTO, M. A. P.; CORREIA, M. M.; GIMENEZ, S. P.
- Digital Performance of OCTO Layout Style on SOI MOSFET at High Temperature Environment(2019-08-25) GALEMBECK, E. H. S.; FLANDRE, D.; RENAUX, C.; Salvador GimenezThis present paper performs an experimental comparative study of the main digital parameters and figures of merit of the octagonal layout style for the planar Silicon-On-Insulator (SOI) Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFET), named OCTO SOI MOSFETs (OSM) in comparison with the typical rectangular one at high temperature environments. The devices were manufactured with the 1 mm SOI (CMOS) technology. The results demonstrate that the OSM is capable of keeping active the Longitudinal Corner Effect (LCE), the PArallel Connection of MOSFETs with Different Channel Lengths Effect (PAMDLE) and the Deactivate the Parasitic MOSFETs of the Bird’s Beak Regions Effect (DEPAMBBRE) at high temperature conditions. Therefore, the OSM is able to continue to have a better electrical performance than the one found in the rectangular SOI MOSFET (RSM) counterparts, regarding the same gate areas and bias conditions. To illustrate, its on-state drain current (ION) and off-state drain current (IOFF) are respectively 186% higher and 64% smaller in relation to its RSM counterparts at high temperature conditions.
- Effect of Interface Traps on the RTS Noise Behavior of Junctionless Nanowires(2020-08-10) PICOLI JUNIOR, M. P.; TREVISOLI, R.; DORIA, R.T.This work presents a study on the effects of single interface traps throughout the Junctionless Nanowire Transistor (JNT). The results are obtained by analyzing the Random Telegraph Signal noise of the device, which consists of an exception of the generation-recombination noise. The results obtained are mostly from numerical simulation, validated through experimental data. As in physical devices, it is impossible to obtain a single trap in specific locations, we have used a distribution of traps with similar characteristics in a way that they behave like a single trap. The results show the behave considering a set of traps distributions, using an exponential model. The traps are distributed from the conduction band to the valence band.
- The Correlation between the NBTI Effect and the Surface Potential and Density of Interface Traps in Junctionless Nanowire Transistors(2020-07-31) GRAZIANO JUNIOR, N.; TREVISOLI, R.; DORIA, R. T.This paper discusses the nature of degradation by NBTI effect in MOS junctionless devices when varying the density of interface traps and surface potential. The data obtained in simulations are compared with results from physical devices and it is demonstrated how the quality of gate oxide affects the performance of such transistors, when the density of traps, the channel width, the doping concentration and the gate bias are varied.
- UTBB MOSFETs Thermal Coupling Analysis in Technological Node Level(2020-07-31) COSTA, F. J.; DORIA, R. T.; Rodrigo Trevisoli DoriaThe main goal of this work is to perform a first-time analysis of the thermal cross-coupling in a system composed by some devices in an integration node degree composed by advanced UTBB SOI MOSFETs through numerical simulations, validated with experimental data from the literature. In this analysis, it could be observed that devices located on the channel length direction provoke a reduced thermal coupling and devices with their drain region next to each other suffer of an increased thermal coupling due to the lumped thermal energy. It also could be observed a degradation in some electrical parameters and in the thermal properties of a device under the influence of surrounded devices biased.
- Substrate Effect Evaluation by the Analysis of Intrinsic Capacitances in SOI UTBB Transistors(2020-05-26) COSTA, F. J.; DORIA, R. T.; Rodrigo Trevisoli DoriaThe main goal of this paper is to present the behavior of the substrate effect in Ultra-Thin Body and Buried Oxide (UTBB) SOI MOSFETs with respect to the back gate bias (VSUB) through DC and AC simulations validated to experimental data. Different ground plane (GP) arrangements have been considered in order to enhance the analysis. It has been shown that the substrate effect is strongly influenced by the reduction of the back gate bias and, that the capacitive coupling of the structure presents a different behavior with respect of each kind of GP configuration as the back gate bias is varied. Finally, it has been shown that the GP below the source and drain regions contributes significantly to the overall capacitive coupling of the transistors.
- Temperature, Silicon Thickness and Intrinsic Length Influence on the Operation of Lateral SOI PIN Photodiodes(2020-08-11) RODRIGUES, EDSON JOSÉ; Michelly De SouzaThis work presents an analysis of the influence of intrinsic length region and the thickness of the silicon film on the performance of lateral thin-film SOI PIN (Silicon on insulator P-I-N photodiodes) when illuminated by low wavelengths, in the blue and ultraviolet (UV) range. The experimental measurements performed with the wavelengths of 396 nm, 413 nm, and 460 nm in a temperature range of 100 K to 400 K showed that the optical responsivity of the SOI PIN photodetectors has larger dependence on the incident wavelength than on the variation of temperature. Two-dimensional numerical simulations showed the same trends as the experimental results as a function of temperature and as a function of wavelength. Numerical simulations were used to investigate the responsivity and total quantum efficiency of PIN SOI photodetectors with intrinsic length region ranging from 5 μm to 30 μm and silicon film thickness ranging between 40 nm to 500 nm. From the results it can be concluded that by properly choosing intrinsic length and silicon film thickness it is possible to optimize PIN SOI photodiodes performance for detecting specific wavelengths that can help defining the best technology for detection of a given wavelength.
- Analysis of Current Mirrors with Asymmetric Self-Cascode Association of SOI MOSFETs through SPICE Simulations(2020-07-31) SILVA, PAULO RODRIGUES; Michelly De Souza
- Analysis of Mobility in Graded-Channel SOI Transistors aiming at Circuit Simulation(2020-07-31) SILVA, LUCAS MOTA BARBOSA DA; PAZ, BRUNA CARDOSO; Michelly De SouzaThis work presents an analysis of the behavior of the effective mobility of graded-channel FD SOI transistors us-ing an Y-Function-based technique. Low field mobility, linear and quadratic attenuation factors were extracted from two-di-mensional numerical simulations. The influence of the length of both channel regions over these parameters was analyzed. The parameters extracted from experimental data were used in a SPICE simulator, showing that it is possible to simulated GC SOI MOSFET using a regular SOI MOSFET model, by adjust-ing its parameters. This approach presents a percentage error smaller than 7.91% for low VDS.