Repositório do Conhecimento Institucional do Centro Universitário FEI
 

Engenharia Elétrica

URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21

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Resultados da Pesquisa

Agora exibindo 1 - 3 de 3
  • Artigo 8 Citação(ões) na Scopus
    Study of matching properties of graded-channel SOI MOSFETs
    (2008-01-05) Michelly De Souza; FLANDRE, D.; Marcelo Antonio Pavanello
    In this paper an overall analysis on the matching properties of Graded-Channel (GC) SOI MOSFETs in comparison to conventional SOI transistors is performed. Experimental results show that GC devices present poorer matching behavior in comparison to conventional SOI counterpart for equal mask channel length, whereas for same effective channel length, almost the same matching behavior. The analytical model for the drain current of GC devices is used to investigate the reasons for this matching worsening. Two-dimensional numerical simulations are used to validate the model-based analysis both in linear and saturation regions.
  • Artigo 17 Citação(ões) na Scopus
    Analog operation temperature dependence of nMOS junctionless transistors focusing on harmonic distortion
    (2011-09-05) Rodrigo Doria; Marcelo Antonio Pavanello; TREVISOLI, R. D.; Michelly De Souza; LEE, C.-W.; FERAIN, I.; AKHAVAN, N. D.; YAN, R.; RAZAVI, P.; YU, R.; FRANTI, A.; COLINGE, J-P.
    This paper performs a comparative study of the analog performance of Junctionless Nanowire Transistors (JNTs) and classical Trigate inversion mode (IM) devices focusing on the harmonic distortion. The study has been carried out in the temperature range of 223 K up to 473 K. The non-linearity or harmonic distortion (HD) has been evaluated in terms of the total and the third order distortions (THD and HD3, respectively) at a fixed input bias and at a targeted output swing. Several parameters important for the HD evaluation have also been observed such as the transconductance to the drain current ratio (gm/IDS), the Early voltage (VEA) and the intrinsic voltage gain (AV). Trigate devices showed maximum AV around room temperature whereas in JNTs the intrinsic voltage gain increases with the temperature. Due to the different AV characteristics, Junctionless transistors present improved HD at higher temperatures whereas inversion mode Trigate devices show better HD properties at room temperature.When both devices are compared, Junctionless transistors present better THD and HD3 with respect to the IM Trigate devices.
  • Artigo 16 Citação(ões) na Scopus
    Temperature and silicon film thickness influence on the operation of lateral SOI PIN photodiodes for detection of short wavelengths
    (2011-09-05) Michelly De Souza; BULTEEL, O.; FLANDRE, D.; Marcelo Antonio Pavanello
    This work presents an analysis of the temperature influence on the performance of a lateral thin-film SOI PIN photodiodes when illuminated by low wavelengths, in the range of blue and ultra-violet (UV). Experimental measurements performed from 100K to 400K showed that the optical responsitivity of SOI PIN photodetectors is affected by temperature change, being reduced at low and moderately high temperatures. Two-dimensional numerical simulations showed the same trends as in the experimental results, and were used both to investigate the physical phenomena responsible for the observed behavior as a function of the temperature as well as to predict the influence of silicon film thickness downscaling on the photodetector performance.