Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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3 resultados
Resultados da Pesquisa
- Analytical compact model for triple gate junctionless MOSFETs(2015-10-13) HERRERA, F. A.; CERDEIRA, A.; PAZ, B. C.; ESTRADA, M.; Marcelo Antonio PavanelloA new compact analytical model for triple gate junctionless transistors JLT is presented considering the capacitances when the fin height is reduced. For its calculation, the capacitance is separated into gate and silicon height capacitance. On the modeling side, threshold voltage, drain current model and short channel effects are modeled considering the influence of variable fin height. Based on our previous developed analytical model for 2D devices, which neglects the fin height effects, a 3D analytical compact model was developed including short channel effects. The 3D model presented is useful for modeling silicon triple gate junctionless transistors. The model validation is done by simulations varying the fin height and channel length.
- Role of the extensions in Double-Gate Junctionless MOSFETs in the drain current at high gate voltage(2015-10-13) CERDEIRA, A.; HERRERA, F. A.; PAZ, B. C.; ESTRADA, M.; Marcelo Antonio PavanelloThis work studies the effect of doping level applied to the extensions on the electrical characteristics of short channel double gate junctionless transistor. Structures with homogeneous doping profile between source and drain contacts and structures with additional doping in the extensions are studied. 2D simulations were performed for structures with doping concentration of 5×1018 and 1019 cm-3, silicon layer thickness of 10 and 15 nm and with/without extensions of 30 nm. Above flat band voltage, the drain current in saturation presents an important decrease for homogeneously doped structures with extensions attributed to the reduction of potentials at high gate voltage. Lower short channel effects, as less threshold voltage roll off and less subthreshold slope take place in this type of structures due to the shift of minimum potential in the extension regions.
- Effective channel length in Junctionless Nanowire Transistors(2015-10-13) TREVISOLLI, R.; Rodrido Doria; Michelly De Souza; Marcelo Antonio PavanelloThe aim of this work is to analyze the influence of the lateral depletion induced by the gate towards the source/drain regions on the effective channel length of Junctionless Nanowire Transistors. The effective channel length increase at the subthreshold regime is analyzed by means of simulations together with experimental results, showing that the JNT can be significantly longer than the gate length.