Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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3 resultados
Resultados da Pesquisa
- Electrical characteristics of n-type vertically stacked nanowires operating up to 600 K(2022-08-05) MARINIELLO, G.; BARRAUD, S.; VINET, M.; CASSE, M.; FAYNOT, O.; CALCADE, J.; Marcelo Antonio Pavanello© 2022 Elsevier LtdThis paper aims at analyzing the electrical characteristics of n-type vertically stacked nanowires with variable fin width, operating in the temperature range of 300–600 K. Basic electrical parameters, such as threshold voltage, subthreshold slope, and carrier mobility are extracted in the linear region, whereas the transconductance, output conductance, and intrinsic voltage gain are extracted in saturation, to access some of device's analog figures of merit. Also, it has been analyzed the DIBL, GIDL, Ion, and Ioff. currents.
- Electrical characterization of stacked SOI nanowires at low temperatures(2022-05-05) RODRIGUES, J. C.; MARINIELLO, G.; CASSE, M.; BARRAUD, S.; VINET, M.; FAYNOT, O.; Marcelo Antonio PavanelloThis work presents the electrical characterization of 2-level vertically stacked nanowire MOSFETs with variable fin widths in the temperature range from 93 K to 400 K. The basic electrical properties, such as threshold voltage, subthreshold slope, and carrier mobility are examined in the linear region with low VDS. In sequence, certain analog figures of merit such as the transconductance, the output conductance, and the voltage gain are assessed in saturation. The threshold voltage variation with temperature is linear and slightly increases for wider devices, which was satisfactorily validated by an analytical model for 3D devices. Additionally, the subthreshold slope remains close to the theoretical limit in the whole range of temperatures. The intrinsic voltage gain is weakly temperature-sensitive in the studied range regardless of the fin width. On the other hand, it increases for narrow devices in all temperatures.
- Study of silicon n- and p-FET SOI nanowires concerning analog performance down to 100 K(2017) Paz B.C.; Casse M.; Barraud S.; Reimbold G.; Vinet M.; Faynot O.; Pavanello M.A.© 2016 Elsevier LtdThis work presents an analysis of the performance of silicon triple gate SOI nanowires aiming the investigation of analog parameters for both long and short channel n-type and p-MOSFETs. Several nanowires with fin width as narrow as 9.5 nm up to quasi-planar MOSFETs 10 μm-wide are analyzed. The fin width influence on the analog parameters is studied for n-type and p-MOSFETs with channel lengths of 10 μm and 40 nm, at room temperature. The temperature influence is analyzed on the analog performance down to 100 K for long channel n-MOSFETs by comparing the quasi-planar device to the nanowire with fin width of 14.5 nm. The intrinsic voltage gain, transconductance and output conductance are the most important figures of merit in this work. An explicit correlation between these figures of merit and the mobility behavior with temperature is demonstrated.