Departamento de Física
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/785
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6 resultados
Resultados da Pesquisa
- Reliability calculation with respect to functional failures induced by radiation in TMR arm cortex-M0 soft-core embedded into SRAM-based FPGA(2019) Benites L.A.C.; Benevenuti F.; De Oliveira A.B.; Kastensmidt F.L.; Added N.; Aguiar V.A.P.; Medina N.H.; Guazzelli M.A.© 2019 IEEE.This paper presents comparative results from fault injection (FI) and heavy ions accelerated irradiation on a Xilinx 7 series static RAM (SRAM)-based field-programmable gate array (FPGA) for a soft-core microprocessor mitigated by triple modular redundancy (TMR) with different levels of granularity. The Arm Cortex-M0 soft-core processor executing two software applications is employed as a case study. The TMR implementation is automatically generated from synthesized netlist and includes coarse and fine grain variants. Apart from the TMR mitigation, the configuration memory scrubbing is used as implemented by the engine natively available on Xilinx 7 series FPGAs. Experiments with FI and heavy ions allow analyzing the effectiveness of the automated TMR mitigation combined with memory scrubbing and also to analyze the consistency of reliability metrics from FI and heavy ions. The dynamic cross section of the design was improved up to 4.5 times according to the implemented TMR granularity and when associated with the configuration memory scrubbing.
- Reliability-Performance Analysis of Hardware and Software Co-Designs in SRAM-Based APSoCs(2018) Tambara L.A.; Kastensmidt F.L.; Rech P.; Lins F.; Medina N.H.; Added N.; Aguiar V.A.P.; Silveira M.A.G.© 1963-2012 IEEE.All programmable system-on-chip (APSoC) devices provide higher system performance and programmable flexibility at lower costs compared to standalone field-programmable gate array devices and processors. Unfortunately, it has been demonstrated that the high complexity and density of APSoCs increase the system's susceptibility to radiation-induced errors. This paper investigates the effects of soft errors on APSoCs at design level through reliability and performance analyses. We explore 28 different hardware and software co-designs varying the workload distribution between hardware and software. We also propose a reliability analysis flow based on fault injection (FI) to estimate the reliability trend of hardware-only and software-only designs and hardware-software co-designs. Results obtained from both radiation experiments and FI campaigns reveal that performance and reliability can be improved up to 117× by offloading the workload of an APSoC-based system to its programmable logic core. We also show that the proposed flow is a precise method to estimate the reliability trend of system designs on APSoCs before radiation experiments.
- Analyzing the Influence of the Angles of Incidence and Rotation on MBU Events Induced by Low LET Heavy Ions in a 28-nm SRAM-Based FPGA(2017) Tonfat J.; Kastensmidt F.L.; Artola L.; Hubert G.; Medina N.H.; Added N.; Aguiar V.A.P.; Aguirre F.; Macchione E.L.A.; Silveira M.A.G.© 1963-2012 IEEE.This paper shows the impact of low linear energy transfer heavy ions on the reliability of 28-nm Bulk static random access memory (RAM) cells from Artix-7 field-programmable gate array. Irradiation tests on the ground showed significant differences in the multiple bit upset cross section of configuration RAM and block RAM memory cells under various angles of incidence and rotation of the device. Experimental data are analyzed at transistor level by using the single-event effect prediction tool called multiscale single-event phenomenon prediction platform coupled with SPICE simulations.
- Analyzing Reliability and Performance Trade-Offs of HLS-Based Designs in SRAM-Based FPGAs under Soft Errors(2017) Tambara L.A.; Tonfat J.; Santos A.; Kastensmidt F.L.; Medina N.H.; Added N.; Aguiar V.A.P.; Aguirre F.; Silveira M.A.G.© 1963-2012 IEEE.The increasing system complexity of FPGA-based hardware designs and shortening of time-to-market have motivated the adoption of new designing methodologies focused on addressing the current need for high-performance circuits. High-Level Synthesis (HLS) tools can generate Register Transfer Level (RTL) designs from high-level software programming languages. These tools have evolved significantly in recent years, providing optimized RTL designs, which can serve the needs of safety-critical applications that require both high performance and high reliability levels. However, a reliability evaluation of HLS-based designs under soft errors has not yet been presented. In this work, the trade-offs of different HLS-based designs in terms of reliability, resource utilization, and performance are investigated by analyzing their behavior under soft errors and comparing them to a standard processor-based implementation in an SRAM-based FPGA. Results obtained from fault injection campaigns and radiation experiments show that it is possible to increase the performance of a processor-based system up to 5,000 times by changing its architecture with a small impact in the cross section (increasing up to 8 times), and still increasing the Mean Workload Between Failures (MWBF) of the system.
- Analysis of SRAM-Based FPGA SEU Sensitivity to Combined EMI and TID-Imprinted Effects(2016) Benfica J.; Green B.; Porcher B.C.; Poehls L.B.; Vargas F.; Medina N.H.; Added N.; De Aguiar V.A.P.; Macchione E.L.A.; Aguirre F.; Silveira M.A.G.; Perez M.; Sofo Haro M.; Sidelnik I.; Blostein J.; Lipovetzky J.; Bezerra E.A.© 2016 IEEE.This work proposes a novel methodology to evaluate SRAM-based FPGA's susceptibility with respect to Single-Event Upset (SEU) as a function of noise on VDD power pins, Total-Ionizing Dose (TID) and TID-imprinted effect on BlockRAM cells. The proposed procedure is demonstrated for SEU measurements on a Xilinx Spartan 3E FPGA operating in an 8 MV Pelletron accelerator for the SEU test with heavy-ions, whereas TID was deposited by means of a Shimadzu XRD-7000 X-ray diffractometer. In order to observe the TID-induced imprint effect inside the BlockRAM cells, a second SEU test with neutrons was performed with Americium/Beryllium (241 AmBe). The noise was injected into the power supply bus according to the IEC 61.000-4-29 standard and consisted of voltage dips with 16.67% and 25% of the FPGA's VDD at frequencies of 10 Hz and 5 kHz, respectively. At the end of the experiment, the combined SEU failure rate, given in error/bit.day, is calculated for the FPGA's BlockRAM cells. The combined failure rate is defined as the average SEU failure rate computed before and after exposition of the FPGA to the TID.
- Reliability on ARM Processors Against Soft Errors Through SIHFT Techniques(2016) Chielle E.; Rosa F.; Rodrigues G.S.; Tambara L.A.; Tonfat J.; Macchione E.; Aguirre F.; Added N.; Medina N.; Aguiar V.; Silveira M.A.G.; Ost L.; Reis R.; Cuenca-Asensi S.; Kastensmidt F.L.© 1963-2012 IEEE.ARM processors are leaders in embedded systems, delivering high-performance computing, power efficiency, and reduced cost. For this reason, there is a relevant interest for its use in the aerospace industry. However, the use of sub-micron technologies has increased the sensitivity to radiation-induced transient faults. Thus, the mitigation of soft errors has become a major concern. Software-Implemented Hardware Fault Tolerance (SIHFT) techniques are a low-cost way to protect processors against soft errors. On the other hand, they cause high overheads in the execution time and memory, which consequently increase the energy consumption. In this work, we implement a set of software techniques based on different redundancy and checking rules. Furthermore, a low-overhead technique to protect the program execution flow is included. Tests are performed using the ARM Cortex-A9 processor. Simulated fault injection campaigns and radiation test with heavy ions have been performed. Results evaluate the trade-offs among fault detection, execution time, and memory footprint. They show significant improvements of the overheads when compared to previously reported techniques.