Departamento de Física
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/785
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4 resultados
Resultados da Pesquisa
- Analysis of FPGA SEU sensitivity to combined effects of conducted EMI and TID(2016-05-17) BENFICA, J.; GREEN, B.; PORCHER, B. C.; POEHLS, L. B.; VARGAS, F.; MEDINA, N. H.; ADDED, N.; AGUIAR, V. A. P. DE; MACCHIONE, E. L. A.; AGUIRRE, F.; Marcilei Aparecida Guazzelli© 2016 IEEE.This work proposes a novel methodology to evaluate SRAM-Based FPGA SEU susceptibility to noise on VDD power pins and total-ionizing dose (TID). The procedure was demonstrated for SEU measurements on a Xilinx Spartan 3E FPGA operating in an 8MV Pelletron accelerator, whereas TID was deposited by means of a Shimadzu XRD-7000 X-ray diffractometer. The injected noise on power supply bus comprised of voltage dips of 16.67% and 25% of VDD at two different frequencies 10Hz and 5kHz, and was performed according to the IEC 61.000-4-29 international standard.
- Analyzing the Influence of using Reconfiguration Memory Scrubber and Hardware Redundancy in a Radiation Hardened FPGA under Heavy Ions(2018-09-05) OLIVEIRA, A.B. DE; BENEVENUT,I F.; BENITES, L. A. C.; RODRIGUES, G. S.; KASTENSMIDT, F. L.; ADDED, N.; AGUIAR, V. A. P.; MEDINA, N. H.; Marcilei Aparecida Guazzelli; DEBARGE, C.© 2018 IEEE.This work investigates the influence of using the built-in configuration memory scrubber and triple modular hardware redundancy in the cross section of a radiation-hardened SRAM-based FPGA from NanoXplore. Different designs versions are investigated under heavy ions for the occurrence of transient errors, failures, and timeouts. The calculated dynamic cross-sections are in agreement with the expected order of magnitude of radiation hardened SRAM-based FPGAs. Results show that the most reliable configuration is using DSPs for the operational logic and applying full design redundancy combined with scrubbing.
- Dynamic heavy ions SEE testing of NanoXplore radiation hardened SRAM-based FPGA: Reliability-performance analysis(2019) OLIVEIRA, A.; BENEVENUTI, F.; BENITES, L.; RODRIGUES, G.; KASTENSMIDT, F.; ADDED, N.; AGUIAR, V.; MEDINA, N.; Marcilei Aparecida Guazzelli; TAMBARA, L.© 2019 Elsevier LtdNanoXplore is the European pioneer vendor to develop ITAR-free radiation-hardened SRAM-based FPGAs. This work is the first to explore dynamic SEE tests in the NG-Medium FPGA device. The reliability-performance analysis of an embedded unmitigated design is performed under heavy ion-induced errors. Moreover, the improvements of additional user level fault-tolerance techniques, such as redundancy and scrubbing, are explored. The design sensitiveness is evaluated through dynamic cross section, mean fluence to failure, and empiric reliability. Results obtained demonstrate the best tradeoff between area, performance, and reliability is achieved combining full design redundancy, periodic scrubbing, arithmetic functions implemented in DSPs, logical resets between executions, and area-oriented application execution.
- Robust convolutional neural networks in sram-based fpgas: A case study in image classification(2021-08-23) BENEVENUTI, F.; KASTENSMIDT, F.; OLIVEIRA, A.; ADDED, N.; AGUIAR, V.; MEDINA, N.; Marcilei Aparecida Guazzelli© 2021, Brazilian Microelectronics Society. All rights reserved.— This work discusses the main aspects of vulnerability and degradation of accuracy of an image classification engine implemented into SRAM-based FPGAs under faults. The image classification engine is an all-convolutional neural-network (CNN) trained with a dataset of traffic sign recognition benchmark. The Caffe and Ristretto frameworks were used for CNN training and fine-tuning while the ZynqNet inference engine was adopted as hardware implementation on a Xilinx 28 nm SRAM-based FPGA. The CNN under test was generated using an evolutive approach based on genetic algorithm. The methodologies for qualifying this CNN under faults is presented and both heavy-ions accelerated irradiation and emulated fault injection were performed. To cross validate results from radiation and fault injection, different implementations of the same CNN were tested using reduced arithmetic precision and protection of user data by Hamming codes, in combination with configuration memory healing by the scrubbing mechanism available in Xilinx FPGA. Some of these alternative implementations increased significantly the mission time of the CNN, when compared to the original ZynqNet operating on 32 bits floating point number, and the experiment suggests areas for further improvements on the fault injection methodology in use.