Departamento de Física
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/785
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4 resultados
Resultados da Pesquisa
- Reducing Soft Error Rate of SoCs Analog-to-Digital Interfaces with Design Diversity Redundancy(2020-03-05) GONZALEZ, C. J.; ADDED, N.; MACCHIONE, E. L. A.; AGUIAR, V. A. P.; KASTENSMIDT, F. G. L.; PUCHNER, H. K.; Marcilei Aparecida Guazzelli; MEDINA, N. H.; BALEN, T. R.© 1963-2012 IEEE.In this article, a commercial programmable system-on-chip (PSoC 5, from Cypress Semiconductor) is tested under heavy-ion irradiation with a focus on the analog-to-digital interface blocks of the system. For this purpose, a data acquisition system (DAS) was programmed into the device under test and protected with a design diversity redundancy technique. This technique implements different levels of diversity (architectural and temporal) by using two different architectures of converters (a Σ Δ converter and two successive approximation register (SAR) converters) operating with distinct sampling rates. The experiment was performed in a vacuum chamber, using a 16O ion beam with 36-MeV energy and sufficient penetration into the silicon to produce an effective linear energy transfer (LET) of 5.5 MeV/mg/cm2 at the active region. The average flux was approximately 350 particles/s/cm2 for 246 min. The individual susceptibility of each converter to single-event effects is evaluated, as well as the whole system cross section. Results show that the proposed technique is effective to mitigate errors originating at the converters since 100% of such errors were corrected by using the diversity redundancy technique. Results also show that the processing unit of the system is susceptible to hangs that can be mitigated using watchdog techniques.
- Reliability-Performance Analysis of Hardware and Software Co-Designs in SRAM-Based APSoCs(2018) Tambara L.A.; Kastensmidt F.L.; Rech P.; Lins F.; Medina N.H.; Added N.; Aguiar V.A.P.; Silveira M.A.G.© 1963-2012 IEEE.All programmable system-on-chip (APSoC) devices provide higher system performance and programmable flexibility at lower costs compared to standalone field-programmable gate array devices and processors. Unfortunately, it has been demonstrated that the high complexity and density of APSoCs increase the system's susceptibility to radiation-induced errors. This paper investigates the effects of soft errors on APSoCs at design level through reliability and performance analyses. We explore 28 different hardware and software co-designs varying the workload distribution between hardware and software. We also propose a reliability analysis flow based on fault injection (FI) to estimate the reliability trend of hardware-only and software-only designs and hardware-software co-designs. Results obtained from both radiation experiments and FI campaigns reveal that performance and reliability can be improved up to 117× by offloading the workload of an APSoC-based system to its programmable logic core. We also show that the proposed flow is a precise method to estimate the reliability trend of system designs on APSoCs before radiation experiments.
- Analyzing the Influence of the Angles of Incidence and Rotation on MBU Events Induced by Low LET Heavy Ions in a 28-nm SRAM-Based FPGA(2017) Tonfat J.; Kastensmidt F.L.; Artola L.; Hubert G.; Medina N.H.; Added N.; Aguiar V.A.P.; Aguirre F.; Macchione E.L.A.; Silveira M.A.G.© 1963-2012 IEEE.This paper shows the impact of low linear energy transfer heavy ions on the reliability of 28-nm Bulk static random access memory (RAM) cells from Artix-7 field-programmable gate array. Irradiation tests on the ground showed significant differences in the multiple bit upset cross section of configuration RAM and block RAM memory cells under various angles of incidence and rotation of the device. Experimental data are analyzed at transistor level by using the single-event effect prediction tool called multiscale single-event phenomenon prediction platform coupled with SPICE simulations.
- Analyzing Reliability and Performance Trade-Offs of HLS-Based Designs in SRAM-Based FPGAs under Soft Errors(2017) Tambara L.A.; Tonfat J.; Santos A.; Kastensmidt F.L.; Medina N.H.; Added N.; Aguiar V.A.P.; Aguirre F.; Silveira M.A.G.© 1963-2012 IEEE.The increasing system complexity of FPGA-based hardware designs and shortening of time-to-market have motivated the adoption of new designing methodologies focused on addressing the current need for high-performance circuits. High-Level Synthesis (HLS) tools can generate Register Transfer Level (RTL) designs from high-level software programming languages. These tools have evolved significantly in recent years, providing optimized RTL designs, which can serve the needs of safety-critical applications that require both high performance and high reliability levels. However, a reliability evaluation of HLS-based designs under soft errors has not yet been presented. In this work, the trade-offs of different HLS-based designs in terms of reliability, resource utilization, and performance are investigated by analyzing their behavior under soft errors and comparing them to a standard processor-based implementation in an SRAM-based FPGA. Results obtained from fault injection campaigns and radiation experiments show that it is possible to increase the performance of a processor-based system up to 5,000 times by changing its architecture with a small impact in the cross section (increasing up to 8 times), and still increasing the Mean Workload Between Failures (MWBF) of the system.