Departamento de Física
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/785
Navegar
4 resultados
Resultados da Pesquisa
- Analysis of COTS FPGA SEU-sensitivity to combined effects of conducted-EMI and TID(2017-07-31) VILLA, P.; BEZERRA, E.; GOERL, R.; POEHLS, L.; VARGA, F.; MEDINA N.; ADDED, N.; DE AGUIAR, V.; MACCHIORE, E.; AGUIRRE, F.; Marcilei Aparecida Guazzelli© 2017 IEEE.The desirable use of Field-Programmable Gate Arrays (FGPAs) in aerospace & defense field has become a general consensus among IC and embedded system designers. Radiation-hardened (rad-hard) electronics used in this domain is regulated under severe and complex political and commercial treaties. In order to refrain from these undesired political and commercial barriers component-off-the-shelf (COTS) FPGAs (despite the fact of their low reliability) have been considered as a promising alternative to replace rad-hard ICs. In this scenario, this paper analyses the Single-Event Upset (SEU) sensitivity of the Microsemi ProASIC3E A3PE1500 COTS FPGA for a combined set of Electromagnetic Interference (EMI) and Total-Ionizing Dose (TID) tests. This component is under pre-qualification process for use in some satellites of the Brazilian Space Program. Experimental results are herein briefly presented and discussed. These results allow us to consider this component as a strong candidate to replace rad-hard FPGAs, if its use is combined with strict system-level fault-tolerant strategies for error detection and correction (EDAC).
- Analyzing the influence of the angles of incidence on SEU and MBU events induced by low LET heavy ions in a 28-nm SRAM-based FPGA(2017) TONFAT, J.; KASTENSMIDT, F. L.; ARTOLA, L.; HUBERT, G.; MEDINA, N. H.; ADDED, N.; AGUIAR, V. A. P.; AGUIRRE, F.; MACCHIONE, E. L. A.; Marcilei Aparecida Guazzelli© 2016 IEEE.This work highlights the impact of low LET heavy ions particles on the reliability of 28-nm Bulk SRAM cells from 4rtix-7 FPGA. Radiation tests showed significant differences in he MBU cross section of configuration (CRAM) and BRAM memory cells under various angles of incidence. Radiation results re compared with simulations at transistor level by using the ioft error tool, MUSCA SEP3 (MUlti-SCAle Single Event henomenon Prediction Platform) coupled with circuit imulations with the aim to analyze the differences of upset ensitivity as a function of layout SRAM. This analysis leads to etermine the correct layout and technology used in the tested PGA. By using the detailed classification of MBU events, it is ossible to analyze the effectiveness of correction mechanisms of he FPGA configuration memory.
- Analyzing the Influence of using Reconfiguration Memory Scrubber and Hardware Redundancy in a Radiation Hardened FPGA under Heavy Ions(2018-09-05) OLIVEIRA, A.B. DE; BENEVENUT,I F.; BENITES, L. A. C.; RODRIGUES, G. S.; KASTENSMIDT, F. L.; ADDED, N.; AGUIAR, V. A. P.; MEDINA, N. H.; Marcilei Aparecida Guazzelli; DEBARGE, C.© 2018 IEEE.This work investigates the influence of using the built-in configuration memory scrubber and triple modular hardware redundancy in the cross section of a radiation-hardened SRAM-based FPGA from NanoXplore. Different designs versions are investigated under heavy ions for the occurrence of transient errors, failures, and timeouts. The calculated dynamic cross-sections are in agreement with the expected order of magnitude of radiation hardened SRAM-based FPGAs. Results show that the most reliable configuration is using DSPs for the operational logic and applying full design redundancy combined with scrubbing.
- Analyzing Reliability and Performance Trade-Offs of HLS-Based Designs in SRAM-Based FPGAs under Soft Errors(2017) Tambara L.A.; Tonfat J.; Santos A.; Kastensmidt F.L.; Medina N.H.; Added N.; Aguiar V.A.P.; Aguirre F.; Silveira M.A.G.© 1963-2012 IEEE.The increasing system complexity of FPGA-based hardware designs and shortening of time-to-market have motivated the adoption of new designing methodologies focused on addressing the current need for high-performance circuits. High-Level Synthesis (HLS) tools can generate Register Transfer Level (RTL) designs from high-level software programming languages. These tools have evolved significantly in recent years, providing optimized RTL designs, which can serve the needs of safety-critical applications that require both high performance and high reliability levels. However, a reliability evaluation of HLS-based designs under soft errors has not yet been presented. In this work, the trade-offs of different HLS-based designs in terms of reliability, resource utilization, and performance are investigated by analyzing their behavior under soft errors and comparing them to a standard processor-based implementation in an SRAM-based FPGA. Results obtained from fault injection campaigns and radiation experiments show that it is possible to increase the performance of a processor-based system up to 5,000 times by changing its architecture with a small impact in the cross section (increasing up to 8 times), and still increasing the Mean Workload Between Failures (MWBF) of the system.