Using statistical student's t-test to qualify the electrical performance of the diamond MOSFETs
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2018-08-31
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PERUZZI, V. V.
DA SILVA, G. A
RENAUX, C.
FLANDRE, D
Salvador Gimenez
DA SILVA, G. A
RENAUX, C.
FLANDRE, D
Salvador Gimenez
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33rd Symposium on Microelectronics Technology and Devices, SBMicro 2018
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PERUZZI, V. V. ; DA SILVA, G. A.; RENAUX, C.; FLANDRE, D.; GIMENEZ, S.Using statistical student's t-test to qualify the electrical performance of the diamond MOSFETs. 33rd Symposium on Microelectronics Technology and Devices, SBMicro 2018, Aug. 2018.
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© 2018 IEEE.This study describes the use of the Student's t-Test to qualify statistically the impact of using the Diamond (hexagonal) layout style in the electrical performance of Silicon-On-Insulator (SOI) MOSFETs. A sample of 360 SOI Metal-Oxide-{Semiconductor Field Effect Transistors, n-type (nMOSFETs) were used to perform this experimental work. Regarding the SOI MOSFETs saturation drain current (IDSsat), the results of this study indicate that the Diamond SOI nMOSFETs for all considered angles present higher IDSsat mean values in comparison to those measured from the standard rectangular SOI MOSFET counterparts, considering that they present the same gate areas, channel width and bias conditions (with a bias condition of 1V between the drain and source and a bias condition of 0.4V between the gate and source). For all the other α angle, that is, 36.9 °, 53.1 °, 90.0 °, 126.9 ° and 143.1 °, the DSnM IDSsat((W/L) mean value is higher than the CSnM IDSsat((W/L) mean value in an order of 51.3%, 37.6%, 40.9%, 19.0% and 10.6%, respectively. Therefore, this statistical approach can be used as a power statistical tool to validate electrical parameters and figures of merit of devices and integrated circuits regarding the nanoelectronics area.