Linearity analysis in double gate Graded-Channel SOI devices applied to 2-MOS MOSFET-C balanced structures
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2008-09-04
Autores
Rodrigo Doria
CERDEIRA, A.
RASKIN, J. P.
FLANDRE, D.
Marcelo Antonio Pavanello
CERDEIRA, A.
RASKIN, J. P.
FLANDRE, D.
Marcelo Antonio Pavanello
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ECS Transactions
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DORIA, R.; CERDEIRA, A.; RASKIN, J. P.; FLANDRE, D.; PAVANELLO, M. A. Linearity analysis in double gate Graded-Channel SOI devices applied to 2-MOS MOSFET-C balanced structures. ECS Transactions, v. 14, n. 1, p. 282-273, Sept,. 2009.
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This paper examines the linearity of 2-MOS MOSFET-C balanced structures using conventional and Graded-Channel (GC) Gate-All-Around (GAA) devices. The distortion analysis has been performed through the evaluation of third order harmonic distortion (HD3). The study has been carried out through experimental results, two-dimensional process and device simulations. Along this work, the best operation bias in terms of HD3 is determined for each analysed device and the couple device that exhibits lower HD3 is pointed out. The use of GC GAA devices in 2-MOS structures has showed to improve the linearity in relation to the conventional GAA. Finally, a discussion over the non-linearities causes is performed clarifying their origins and the improvement provided by the adoption of GC GAA devices in 2-MOS structures. © The Electrochemical Society.