Estudo da implementação de um escalonador baseado no algoritmo earliest-deadline-first por hardware para o IHM-PLASMA usando conceitos de processamento paralelo
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Tipo de produção
Dissertação
Data
2022
Autores
Krause, Igor
Orientador
Gimenez, Salvador Pinillos
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Citação
KRAUSE, Igor. Estudo da implementação de um escalonador baseado no algoritmo earliest-deadline-first por hardware para o IHM-PLASMA usando conceitos de processamento paralelo. 2022: 145 p. Dissertação (Mestrado em Engenharia Elétrica) - Centro Universitário FEI - São Bernardo do Campo, 2022. Disponível em: https://doi.org/10.31414/EE.2022.D.131427.
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Palavras-chave
arquitetura de computador,microprocessadores,algoritmo de escalonamento,engenharia elétrica
Resumo
Este projeto de pesquisa tem por objetivo implementar um novo bloco escalonador de
tarefas de um sistema operacional baseado em tarefas, que foi implementado por hardware,
para executar o processamento paralelo de instruções, intitulado Interlocked-Hardware-
Microkernel (IHM), que é capaz de realizar a troca de tarefas em apenas dois ciclos de relógio
(clock), a fim de aumentar a eficiência do processamento das instruções do microprocessador
Plasma, que apresenta arquitetura do tipo Reduced Instruction Set Computer (RISC),
utilizando-se o mínimo de recursos de hardware possível.
Inicialmente este trabalho focou no estudo do microprocessador Plasma e
posteriormente no estudo desse mesmo componente com a implementação do IHM em sua
arquitetura. Foram estudados e documentados, de forma detalhada, o funcionamento e a
arquitetura de todos os blocos básicos que compõem o sistema IHM. É esperado que outros
projetistas de hardware possam se beneficiar com este projeto de pesquisa para implementar
essa mesma estratégia de processamento paralelo de instruções em outros microprocessadores
com a arquitetura RISC que executam sistemas operacionais baseados em tarefas.
O novo bloco escalonador que foi incorporado ao IHM foi implementado com o
algoritmo chamado Earliest-Deadline-First (EDF), que tende a tornar o sistema operacional
baseado em tarefas (Hard real-time Systems) ainda mais eficiente que aqueles que são
implementados com outros algoritmos, segundo a literatura atual.
Essa nova solução de hardware realizada por este trabalho de pesquisa para o IHM foi
simulada e analisada utilizando-se o Simulador Quartus Prime da Intel® e testado num kit
didático com Field-Programmable Gate Array (FPGA) a fim de verificar o seu
comportamento em termos de processamento de instruções em relação ao microprocessador
Plasma original que usa um sistema operacional baseado em tarefas por software.
Os resultados experimentais repetiram os dados da tese de Leandro P. Dantas de que o
sistema IHM se torna mais eficiente quanto mais trocas de tarefas tem no sistema. Eles
também mostraram que o papel do sistema IHM de realizar o escalonamento de tarefas
economiza mais tempo da CPU (1015 ciclos de clock com algoritmo utilizado neste estudo)
do que o papel de realizar a troca de contexto (140 ciclos de clock), o que não foi observado
na tese de Leandro P. Dantas
This scientific research aims to implement a new task scheduler block of a task-based operational system, which was implemented by hardware, to execute the parallel processing of instructions, entitled Interlocked-Hardware-Microkernel (IHM), which is capable of perform task-switches in just 2 clock cycles, in order to increasing the efficiency of instructions processing of Plasma microcontroller, that features Reduced Instruction Set Computer (RISC) architecture, using the minimum amount of hardware possible. Initially this work focused in the study of Plasma microcontroller and posteriorly in the study of this same component with the implementation of IHM in its architecture. The functioning and the architecture of all basic blocks that compose the IHM system were studied and documented in detail. It’s expected that other hardware designers may benefit with this scientific research to implement that same parallel processing of instructions strategy in other RISC architecture microcontrollers that run task-based operational systems. The new scheduler block which was incorporated into the IHM was implemented with the algorithm called Earliest-Deadline-First (EDF), which tends to make the task-based operational system (Hard real-time Systems) even more efficient than the ones implemented with other algorithms, according to the current literature. This new hardware solution proposed by this scientific research for the IHM was simulated and analyzed using the Quartus Prime Simulator from Intel® and tested in a didactic kit with Field-Programmable Gate Array (FPGA) in order to verify your behavior in terms of instructions processing regarding the original Plasma microcontroller that uses a task-based operational system by software. The experimental results repeat the data from Leandro P. Danta’s thesis that the IHM system becomes more efficient the more a system performs task switches. They also show that the role of performing task scheduling of the IHM system saves more clock cycles from the CPU (1015 clock cycles with the algorithm used in this study) than the role of performing the context switching (140 clock cycles), which wasn’t observed at Leandro P. Danta’s thesis
This scientific research aims to implement a new task scheduler block of a task-based operational system, which was implemented by hardware, to execute the parallel processing of instructions, entitled Interlocked-Hardware-Microkernel (IHM), which is capable of perform task-switches in just 2 clock cycles, in order to increasing the efficiency of instructions processing of Plasma microcontroller, that features Reduced Instruction Set Computer (RISC) architecture, using the minimum amount of hardware possible. Initially this work focused in the study of Plasma microcontroller and posteriorly in the study of this same component with the implementation of IHM in its architecture. The functioning and the architecture of all basic blocks that compose the IHM system were studied and documented in detail. It’s expected that other hardware designers may benefit with this scientific research to implement that same parallel processing of instructions strategy in other RISC architecture microcontrollers that run task-based operational systems. The new scheduler block which was incorporated into the IHM was implemented with the algorithm called Earliest-Deadline-First (EDF), which tends to make the task-based operational system (Hard real-time Systems) even more efficient than the ones implemented with other algorithms, according to the current literature. This new hardware solution proposed by this scientific research for the IHM was simulated and analyzed using the Quartus Prime Simulator from Intel® and tested in a didactic kit with Field-Programmable Gate Array (FPGA) in order to verify your behavior in terms of instructions processing regarding the original Plasma microcontroller that uses a task-based operational system by software. The experimental results repeat the data from Leandro P. Danta’s thesis that the IHM system becomes more efficient the more a system performs task switches. They also show that the role of performing task scheduling of the IHM system saves more clock cycles from the CPU (1015 clock cycles with the algorithm used in this study) than the role of performing the context switching (140 clock cycles), which wasn’t observed at Leandro P. Danta’s thesis