Low temperature and channel engineering influence on harmonic distortion of SOI nMOSFETs for analog applications
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2005-05-20
Autores
Marcelo Antonio Pavanello
CERDEIRA, A.
ALEMAN, M. A.
Joao Antonio Martino
VANCAILLE, L.
FLANDRE, D.
CERDEIRA, A.
ALEMAN, M. A.
Joao Antonio Martino
VANCAILLE, L.
FLANDRE, D.
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Proceedings - Electrochemical Society
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PAVANELLO, M. A.; CERDEIRA, A.; ALEMAN, M. A.; MARTINO, J. A.; VANCAILLE, L.;FLANDRE, D. Low temperature and channel engineering influence on harmonic distortion of SOI nMOSFETs for analog applications. Proceedings - Electrochemical Society, v. PV 2005-03, p. 125-130, mayo, 2005.
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An evaluation of the harmonic distortion in conventional and graded-channel SOI MOSFETs is performed from room temperature down to 90 K. The total harmonic distortion as a function of the transconductance over drain current ratio has been adopted as figure of merit. It is shown that the total harmonic distortion increases as the input voltage rises and the temperature is lowered. The use of lateral channel engineering in graded-channel transistors appreciably reduces the total harmonic distortion. The dependence of harmonic distortion on length of the lightly doped region is very weak.