Intrinsic gate capacitances of n-type junctionless nanowire transistors using a three-dimensional device simulation and experimental measurements

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dc.contributor.authorMARINIELLO, G.
dc.contributor.authorRodrido Doria
dc.contributor.authorTREVISOLI, R. D.
dc.contributor.authorMichelly De Souza
dc.contributor.authorMarcelo Antonio Pavanello
dc.contributor.authorOrcidhttps://orcid.org/0000-0003-1361-3650
dc.contributor.authorOrcidhttps://orcid.org/0000-0001-6472-4807
dc.contributor.authorOrcidhttps://orcid.org/0000-0003-4448-4337
dc.date.accessioned2022-01-12T22:02:48Z
dc.date.available2022-01-12T22:02:48Z
dc.date.issued2012-09-02
dc.description.abstractJunctionless Nanowire transistors have been recently proposed as an alternative to overcome the short channel effect caused by the reduction of the transistors dimensions. These devices behave like a gated resistor due to the lack of the p-n junctions in the channel/ source and channel/drain regions. The influence of doping concentration, silicon width, silicon height and gate oxide thickness on the intrinsic gate capacitances are presented in this paper by using three-dimensional numerical simulations and experimental results of fabricated devices. Also the influence of the applied drain bias in the components of the intrinsic gate capacitances is addressed. © The Electrochemical Society.
dc.description.firstpage231
dc.description.issuenumber1
dc.description.lastpage239
dc.description.volume49
dc.identifier.citationMARINIELLO, G.; DORIA, R.; TREVISOLI, R. D.; DE SOUZA, M.; PAVANELLO, M. A. Intrinsic gate capacitances of n-type junctionless nanowire transistors using a three-dimensional device simulation and experimental measurements. ECS Transactions, v. 49, n. 1, p. 231-239, 2012.
dc.identifier.doi10.1149/04901.0231ecst
dc.identifier.issn1938-6737
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/4160
dc.relation.ispartofECS Transactions
dc.rightsAcesso Restrito
dc.titleIntrinsic gate capacitances of n-type junctionless nanowire transistors using a three-dimensional device simulation and experimental measurements
dc.typeArtigo de evento
fei.scopus.citations0
fei.scopus.eid2-s2.0-84875836423
fei.scopus.subjectDoping concentration
fei.scopus.subjectFabricated device
fei.scopus.subjectGate oxide thickness
fei.scopus.subjectIntrinsic gate capacitance
fei.scopus.subjectNanowire transistors
fei.scopus.subjectShort-channel effect
fei.scopus.subjectThree dimensional device simulations
fei.scopus.subjectThree-dimensional numerical simulations
fei.scopus.updated2025-01-01
fei.scopus.urlhttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84875836423&origin=inward
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