Digital Performance of OCTO Layout Style on SOI MOSFET at High Temperature Environment

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dc.contributor.authorGALEMBECK, E. H. S.
dc.contributor.authorFLANDRE, D.
dc.contributor.authorRENAUX, C.
dc.contributor.authorSalvador Gimenez
dc.contributor.authorOrcidhttps://orcid.org/0000-0002-3616-9559
dc.date.accessioned2021-11-25T23:16:39Z
dc.date.available2021-11-25T23:16:39Z
dc.date.issued2019-08-25
dc.description.abstractThis present paper performs an experimental comparative study of the main digital parameters and figures of merit of the octagonal layout style for the planar Silicon-On-Insulator (SOI) Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFET), named OCTO SOI MOSFETs (OSM) in comparison with the typical rectangular one at high temperature environments. The devices were manufactured with the 1 mm SOI (CMOS) technology. The results demonstrate that the OSM is capable of keeping active the Longitudinal Corner Effect (LCE), the PArallel Connection of MOSFETs with Different Channel Lengths Effect (PAMDLE) and the Deactivate the Parasitic MOSFETs of the Bird’s Beak Regions Effect (DEPAMBBRE) at high temperature conditions. Therefore, the OSM is able to continue to have a better electrical performance than the one found in the rectangular SOI MOSFET (RSM) counterparts, regarding the same gate areas and bias conditions. To illustrate, its on-state drain current (ION) and off-state drain current (IOFF) are respectively 186% higher and 64% smaller in relation to its RSM counterparts at high temperature conditions.
dc.description.firstpage1
dc.description.issuenumber2
dc.description.lastpage8
dc.description.volume14
dc.identifier.citationGALEMBECK, E. H. S.; FLANDRE, D.; RENAUX, C.; GIMENEZ, S. P. Digital performance of OCTO layout style on SOI MOSFET at high temperature environment. JICS. JOURNAL OF INTEGRATED CIRCUITS AND SYSTEMS (ED. PORTUGUÊS), v. 14, n. 2, p. 1-8, 2019.
dc.identifier.doi10.29292/jics.v14i2.34
dc.identifier.issn1872-0234
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/3482
dc.relation.ispartofJICS. JOURNAL OF INTEGRATED CIRCUITS AND SYSTEMS (ED. PORTUGUÊS)
dc.rightsAcesso Aberto
dc.rights.licenseOpen Journal Systems "Este é um artigo publicado em acesso aberto sob uma licença de código aberto (GPL v2). Fonte: https://jics.org.br/ojs/index.php/JICS/article/view/34. Acesso em: 25 nov. 2021.
dc.subjectNews styles layout
dc.subjectOCTO layout style
dc.subjecthigh temperature environment
dc.subjectDigital Parameters
dc.subjectLCE
dc.subjectDEPAMBRE
dc.subjectPAMDLE effects
dc.titleDigital Performance of OCTO Layout Style on SOI MOSFET at High Temperature Environmentpt_BR
dc.typeArtigopt_BR
fei.scopus.citations7
fei.scopus.eid2-s2.0-85076531299
fei.scopus.updated2023-11-01
fei.source.urlhttps://jics.org.br/ojs/index.php/JICS/article/view/34
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