Electrical characterization of vertically stacked p-FET SOI nanowires
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3
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2018
Autores
Cardoso Paz B.
Casse M.
Barraud S.
Reimbold G.
Vinet M.
Faynot O.
Antonio Pavanello M.
Casse M.
Barraud S.
Reimbold G.
Vinet M.
Faynot O.
Antonio Pavanello M.
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Solid-State Electronics
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CARDOSO PAZ, BRUNA; CASSÉ, MIKAËL; BARRAUD, SYLVAIN; REIMBOLD, GILLES; VINET, MAUD; FAYNOT, OLIVIER; ANTONIO PAVANELLO, MARCELO. Electrical characterization of vertically stacked p-FET SOI nanowires. SOLID-STATE ELECTRONICS, v. 141, p. 84-91, 2018.
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© 2017 Elsevier LtdThis work presents the performance and transport characteristics of vertically stacked p-type MOSFET SOI nanowires (NWs) with inner spacers and epitaxial growth of SiGe raised source/drain. The conventional procedure to extract the effective oxide thickness (EOT) and Shift and Ratio Method (S&R) have been adapted and validated through tridimensional numerical simulations. Electrical characterization is performed for NWs with [1 1 0]- and [1 0 0]-oriented channels, as a function of both fin width (WFIN) and channel length (L). Results show a good electrostatic control and reduced short channel effects (SCE) down to 15 nm gate length, for both orientations. Effective mobility is found around two times higher for [1 1 0]- in comparison to [1 0 0]-oriented NWs due to higher holes mobility contribution in (1 1 0) plan. Improvements obtained on ION/IOFF by reducing WFIN are mainly due to subthreshold slope decrease, once small and none mobility increase is obtained for [1 1 0]- and [1 0 0]-oriented NWs, respectively.