Subthreshold Operation of Self-Cascode Structure Using UTBB FD SOI Planar MOSFETs

Página do item simplificado
dc.contributor.authorD'OLIVEIRA, L. M.
dc.contributor.authorKILCHYTSKA, V.
dc.contributor.authorPLANES, N.
dc.contributor.authorFLANDRE, D.
dc.contributor.authorMichelly De Souza
dc.contributor.authorOrcidhttps://orcid.org/0000-0001-6472-4807
dc.date.accessioned2022-01-12T21:55:59Z
dc.date.available2022-01-12T21:55:59Z
dc.date.issued2019-10-17
dc.description.abstract© 2019 IEEE.This paper presents an experimental analysis of the analog characteristics of self-cascode structures composed by 28 nm technological node ultra-thin body and BOX fully-depleted silicon-on-insulator planar MOSFETs, focusing on the subthreshold operation regime. Apart from the increased gain promoted by the reduction of front gate voltage, there is further improvement when the back-gate bias is used to reduce the threshold voltage of transistor close to the drain of the composite device, making this structure a promising option for low-power low-voltage (LPLV) analog applications.
dc.identifier.citationD'OLIVEIRA, L. M.; KILCHYTSKA, V.; PLANES, N.; FLANDRE, D.; DE SOUZA, M. Subthreshold Operation of Self-Cascode Structure Using UTBB FD SOI Planar MOSFETs. 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019, Oct. 2019.
dc.identifier.doi10.1109/S3S46989.2019.9320715
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/3694
dc.relation.ispartof2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019
dc.rightsAcesso Restrito
dc.subject.otherlanguageasymmetric structure
dc.subject.otherlanguagecomposite transistor
dc.subject.otherlanguagelow-power
dc.subject.otherlanguageself-cascode
dc.subject.otherlanguageSOI MOSFET
dc.subject.otherlanguagesubthreshold
dc.subject.otherlanguageUTBB
dc.titleSubthreshold Operation of Self-Cascode Structure Using UTBB FD SOI Planar MOSFETs
dc.typeArtigo de evento
fei.scopus.citations0
fei.scopus.eid2-s2.0-85100861044
fei.scopus.subjectAnalog applications
fei.scopus.subjectBack-gate bias
fei.scopus.subjectExperimental analysis
fei.scopus.subjectFully depleted silicon-on-insulator
fei.scopus.subjectGate voltages
fei.scopus.subjectLow power Low voltages
fei.scopus.subjectSubthreshold operation
fei.scopus.subjectUltra thin body and boxes
fei.scopus.updated2025-01-01
fei.scopus.urlhttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85100861044&origin=inward
Arquivos
Coleções
Artigos