Compact core model for Symmetric Double-Gate Junctionless Transistors

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dc.contributor.authorCerdeira A.
dc.contributor.authorAvila F.
dc.contributor.authorIniguez B.
dc.contributor.authorDe Souza M.
dc.contributor.authorPavanello M.A.
dc.contributor.authorEstrada M.
dc.date.accessioned2019-08-19T23:45:11Z
dc.date.available2019-08-19T23:45:11Z
dc.date.issued2014
dc.description.abstractA new charge-based compact analytical model for Symmetric Double-Gate Junctionless Transistors is presented. The model is physically-based and considers both the depletion and accumulation operating conditions including the series resistance effects. Most model parameters are related to physical magnitudes and the extraction procedure for each of them is well established. The model provides an accurate continuous description of the transistor behavior in all operating conditions. Among important advantages with respect to previous models are the inclusion of the effect of the series resistance and the fulfilment of being symmetrical with respect to drain voltage equal to zero. It is validated with simulations for doping concentrations of 5 × 10 18 and 1 × 1019 cm-3, as well as for layer thickness of 10 and 15 nm, allowing normally-off operation. © 2014 Elsevier B.V.
dc.description.firstpage91
dc.description.lastpage97
dc.description.volume94
dc.identifier.citationCERDEIRA, Antonio; AVILA, F.; INIGUEZ, Benjamin; DE SOUZA, Michelly; PAVANELLO, Marcelo A.; CUETO, Magali Estrada. Compact core model for Symmetric Double-Gate Junctionless Transistors. Solid-State Electronics, v. 94, p. 91-97, 2014.
dc.identifier.doi10.1016/j.sse.2014.02.011
dc.identifier.issn0038-1101
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/1102
dc.relation.ispartofSolid-State Electronics
dc.rightsAcesso Restrito
dc.subject.otherlanguageAccumulation JLT
dc.subject.otherlanguageAnalytical junctionless transistor model
dc.subject.otherlanguageDepletion JLT
dc.subject.otherlanguageDouble-Gate Junctionless Transistor model
dc.subject.otherlanguageJLT
dc.titleCompact core model for Symmetric Double-Gate Junctionless Transistors
dc.typeArtigo
fei.scopus.citations23
fei.scopus.eid2-s2.0-84897860861
fei.scopus.subjectAccumulation JLT
fei.scopus.subjectDepletion JLT
fei.scopus.subjectDoping concentration
fei.scopus.subjectExtraction procedure
fei.scopus.subjectJLT
fei.scopus.subjectJunctionless transistors
fei.scopus.subjectOperating condition
fei.scopus.subjectSeries resistance effects
fei.scopus.updated2024-03-04
fei.scopus.urlhttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84897860861&origin=inward
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