An Experimental Evaluation of Fin Width and Low-Temperature Influence on GIDL in Stacked SOI Nanowires

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dc.contributor.authorMichelly De Souza
dc.contributor.authorRODRIGUES, J. C.
dc.contributor.authorMARINIELLO, G.
dc.contributor.authorCASSE, M.
dc.contributor.authorBARRAUD, S.
dc.contributor.authorVINET, M.
dc.contributor.authorFAYNOT, O.
dc.contributor.authorMarcelo Antonio Pavanello
dc.contributor.authorOrcidhttps://orcid.org/0000-0001-6472-4807
dc.contributor.authorOrcidhttps://orcid.org/0000-0003-1361-3650
dc.date.accessioned2022-11-01T06:04:24Z
dc.date.available2022-11-01T06:04:24Z
dc.date.issued2022
dc.description.abstract© 2022 IEEE.In this work, an experimental evaluation of the gate-induced drain leakage (GIDL) of vertically stacked SOI nanowire (NW) FETs is carried out, as a function of temperature for the first time. It is shown that at room temperature, NW width decrease improves gate coupling favoring longitudinal band-to-band-tunneling, which increases normalized GIDL current. The increase of GIDL current with fin narrowing becomes more pronounced with temperature reduction. The influence of fin width has been evaluated, showing that GIDL variation with temperature depends on the device geometry.
dc.identifier.citationDE SOUZA, M.; RODRIGUES, J. C.; MARINIELLO, G.; CASSE, M.; BARRAUD, S.; VINET, M.; FAYNOT, O.; PAVANELLO, M. A. An Experimental Evaluation of Fin Width and Low-Temperature Influence on GIDL in Stacked SOI Nanowires. IEEE 15th Workshop on Low Temperature Electronics, WOLTE 2022 - Conference Proceedings, jUN. 2022.
dc.identifier.doi10.1109/WOLTE55422.2022.9882780
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/4629
dc.relation.ispartofIEEE 15th Workshop on Low Temperature Electronics, WOLTE 2022 - Conference Proceedings
dc.rightsAcesso Restrito
dc.subject.otherlanguageGIDL
dc.subject.otherlanguagelow temperature
dc.subject.otherlanguageSOI
dc.subject.otherlanguagestacked nanowire transistor
dc.titleAn Experimental Evaluation of Fin Width and Low-Temperature Influence on GIDL in Stacked SOI Nanowires
dc.typeArtigo de evento
fei.scopus.citations1
fei.scopus.eid2-s2.0-85139202942
fei.scopus.subjectExperimental evaluation
fei.scopus.subjectFin widths
fei.scopus.subjectGate induced drain leakage currents
fei.scopus.subjectGate induced drain leakages
fei.scopus.subjectLows-temperatures
fei.scopus.subjectNanowire FET
fei.scopus.subjectNanowire transistors
fei.scopus.subjectSOI
fei.scopus.subjectStacked nanowire transistor
fei.scopus.subjectTemperature influence
fei.scopus.updated2024-07-01
fei.scopus.urlhttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85139202942&origin=inward
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