Influence of geometrical parameters on the DC analog behavior of the asymmetric self-cascode FD SOI nMOSFETs

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dc.contributor.authorAssalti R.
dc.contributor.authorFlandre D.
dc.contributor.authorde Souza M.
dc.date.accessioned2019-08-19T23:45:17Z
dc.date.available2019-08-19T23:45:17Z
dc.date.issued2018
dc.description.abstract© 2018, Brazilian Microelectronics Society. All rights reserved.This paper assesses the DC analog performance of a composite transistor named Asymmetric Self-Cascode structure, which is formed by two Fully Depleted SOI nMOSFETs connected in series with shortened gates. The in-fluence of geometrical parameters, such as different channel widths and lengths on the transistors at source and drain sides is evaluated through three-dimensional numerical simulations, which have been firstly adjusted to the experimental measure-ments. The transconductance, output conductance, Early volt-age and intrinsic voltage gain have been used as figures of merit to explore the advantages of the composite transistor. From the obtained results, the largest intrinsic voltage gain has been ob-tained by using longer channel lengths for both transistors, with narrower device close to the source and wider transistor near to the drain.
dc.description.firstpage1
dc.description.issuenumber2
dc.description.lastpage7
dc.description.volume13
dc.identifier.citationASSALTI, Rafael; FLANDRE, Denis; de Souza, Michelly. Influence of Geometrical Parameters on the DC Analog Behavior of the Asymmetric Self-Cascode FD SOI nMOSFETs. JICS. JOURNAL OF INTEGRATED CIRCUITS AND SYSTEMS (ED. PORTUGUÊS), v. 13, n. 2, p. 1-7, 2018.
dc.identifier.doi10.29292/jics.v13i2.15
dc.identifier.issn1872-0234
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/1182
dc.relation.ispartofJournal of Integrated Circuits and Systems
dc.rightsAcesso Aberto
dc.subject.otherlanguageAnalog performance
dc.subject.otherlanguageAsymmetric self-cascode
dc.subject.otherlanguageComposite transistor
dc.subject.otherlanguageFD SOI nMOSFET
dc.titleInfluence of geometrical parameters on the DC analog behavior of the asymmetric self-cascode FD SOI nMOSFETs
dc.typeArtigo
fei.scopus.citations2
fei.scopus.eid2-s2.0-85062820550
fei.scopus.updated2024-03-04
fei.scopus.urlhttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85062820550&origin=inward
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