Analysis of gate capacitance of n-type junctionless transistors using three-dimensional device simulations

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dc.contributor.authorMARINIELLO, G.
dc.contributor.authorRodrido Doria
dc.contributor.authorMichelly De Souza
dc.contributor.authorMarcelo Antonio Pavanello
dc.contributor.authorTREVISOLI, R. D. G.
dc.date.accessioned2022-01-12T22:02:30Z
dc.date.available2022-01-12T22:02:30Z
dc.date.issued2012-03/17
dc.description.abstractJunctionless transistors can be an excellent alternative for extremely scaled MOSFETs as they present a good behavior with no doping gradients between channel and source/drain regions. This paper aims at analyzing the gate capacitance (C gg) of junctionless transistors dependence with the three most important technological parameters for these devices: doping concentration (N D), fin width (W fin) and fin height (H fin). © 2012 IEEE.
dc.identifier.citationMARINIELLO, G.; DORIA, R.; DE SOUZA, M.; PAVANELLO, M. A. ; TREVISOLI, R. D. Analysis of gate capacitance of n-type junctionless transistors using three-dimensional device simulations. 2012 8th International Caribbean Conference on Devices, Circuits and Systems, ICCDCS 2012. March. 2012.
dc.identifier.doi10.1109/ICCDCS.2012.6188946
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/4139
dc.relation.ispartof2012 8th International Caribbean Conference on Devices, Circuits and Systems, ICCDCS 2012
dc.rightsAcesso Restrito
dc.subject.otherlanguageGate Capacitance
dc.subject.otherlanguageJunctionless Devices
dc.titleAnalysis of gate capacitance of n-type junctionless transistors using three-dimensional device simulations
dc.typeArtigo de evento
fei.scopus.citations13
fei.scopus.eid2-s2.0-84860999336
fei.scopus.subjectDoping concentration
fei.scopus.subjectDoping gradients
fei.scopus.subjectFin height
fei.scopus.subjectFin widths
fei.scopus.subjectGate capacitance
fei.scopus.subjectJunctionless
fei.scopus.subjectMOSFETs
fei.scopus.subjectSource/drain regions
fei.scopus.subjectTechnological parameters
fei.scopus.subjectThree dimensional device simulations
fei.scopus.updated2025-02-01
fei.scopus.urlhttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84860999336&origin=inward
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