Liquid helium temperature analog operation of asymmetric self-cascode FD SOI MOSFETs

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dc.contributor.advisorDE SOUZA, M.; KILCHTYSKA, V.; FLANDRE, D.; PAVANELLO, M. A. Liquid helium temperature analog operation of asymmetric self-cascode FD SOI MOSFETs. Proceedings - IEEE International SOI Conference, Oct., 2012.
dc.contributor.authorMichelly De Souza
dc.contributor.authorKILCHTYSKA, V.
dc.contributor.authorFLANDRE, D.
dc.contributor.authorMarcelo Antonio Pavanello
dc.contributor.authorOrcidhttps://orcid.org/0000-0003-1361-3650
dc.contributor.authorOrcidhttps://orcid.org/0000-0001-6472-4807
dc.date.accessioned2022-01-12T22:02:12Z
dc.date.available2022-01-12T22:02:12Z
dc.date.issued2012-10-04
dc.description.abstractFully Depleted (FD) SOI technology is well known to provide improved analog performance of CMOS transistors [1, 2]. However, FD SOI transistors may suffer from parasitic bipolar effects (PBE) that cause the degradation of the output conductance [3]. The use of cascode transistors with common gate (making a self-cascode-SC topology) has been shown to reduce the output conductance of MOSFETs, while keeping some advantages of long-channel transistors [4]. Fig. 1 represents the self-cascode transistor, composed by transistors MS and MD, with channel lengths LS and LD, and threshold voltages VT, S and VT, D, respectively (with VT, S = VT, D in the symmetric SC-S-SC). Recent works [5, 6] showed that the use of different threshold voltages (VT) for MS and MD (so-called asymmetric self-cascode-A-SC) is able to further enhance the analog properties of SC n-and pMOS transistors, in comparison to the S-SC, at room temperature (RT). In this paper the enhanced analog performance of asymmetric SC structure is experimentally demonstrated at deep cryogenic environments emphasizing its capability to minimize (or even suppress) PBE in FD SOI n-and p-type MOSFETs at liquid helium temperature (LHT), where this effect is more pronounced [7]. © 2012 IEEE.
dc.identifier.doi10.1109/SOI.2012.6404377
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/4119
dc.relation.ispartofProceedings - IEEE International SOI Conference
dc.rightsAcesso Restrito
dc.titleLiquid helium temperature analog operation of asymmetric self-cascode FD SOI MOSFETs
dc.typeArtigo de evento
fei.scopus.citations5
fei.scopus.eid2-s2.0-84873555910
fei.scopus.subjectAnalog operations
fei.scopus.subjectAnalog performance
fei.scopus.subjectBipolar effects
fei.scopus.subjectCascode transistors
fei.scopus.subjectChannel length
fei.scopus.subjectCMOS transistors
fei.scopus.subjectCommon gates
fei.scopus.subjectCryogenic environment
fei.scopus.subjectFully depleted
fei.scopus.subjectLiquid helium temperature
fei.scopus.subjectMOSFETs
fei.scopus.subjectOutput conductance
fei.scopus.subjectP-type
fei.scopus.subjectpMOS transistors
fei.scopus.subjectRoom temperature
fei.scopus.subjectSC structures
fei.scopus.subjectSelf-cascode
fei.scopus.subjectSOI technology
fei.scopus.subjectSOI transistors
fei.scopus.subjectSOI-MOSFETs
fei.scopus.updated2024-07-01
fei.scopus.urlhttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84873555910&origin=inward
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