Adaption of triple gate junctionless MOSFETs analytical compact model for accurate circuit design in a wide temperature range
dc.contributor.author | CERDEIRA, A. | |
dc.contributor.author | AVILA-HERRERA, F. | |
dc.contributor.author | ESTRADA, M. | |
dc.contributor.author | DORIA, R. T. | |
dc.contributor.author | Marcelo Antonio Pavanello | |
dc.contributor.authorOrcid | https://orcid.org/0000-0003-1361-3650 | |
dc.date.accessioned | 2022-01-12T21:57:22Z | |
dc.date.available | 2022-01-12T21:57:22Z | |
dc.date.issued | 2018-03-19 | |
dc.description.abstract | This paper presents the necessary adaptions on the proposed compact analytical model of triple gate junctionless nanowire transistors for accurate description of device electrical characteristics in a wide temperature range. The model validation is performed by comparison against experimental results showing very good agreement, with continuous current and its derivatives in all regions of operation and temperatures. | |
dc.description.firstpage | 1 | |
dc.description.lastpage | 4 | |
dc.description.volume | 2018-January | |
dc.identifier.citation | CERDEIRA, A.; AVILA-HERRERA, F.; ESTRADA, M.; DORIA, R. T.; PAVANELLO, M. A. Adaption of triple gate junctionless MOSFETs analytical compact model for accurate circuit design in a wide temperature range. 2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2018, p. 1-4, 2018 | |
dc.identifier.doi | 10.1109/ULIS.2018.8354743 | |
dc.identifier.uri | https://repositorio.fei.edu.br/handle/FEI/3788 | |
dc.relation.ispartof | 2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2018 | |
dc.rights | Acesso Restrito | |
dc.subject.otherlanguage | compact model | |
dc.subject.otherlanguage | Junctioless nanowire transistor | |
dc.subject.otherlanguage | temperature | |
dc.title | Adaption of triple gate junctionless MOSFETs analytical compact model for accurate circuit design in a wide temperature range | |
dc.type | Artigo de evento | |
fei.scopus.citations | 0 | |
fei.scopus.eid | 2-s2.0-85050953816 | |
fei.scopus.subject | Circuit designs | |
fei.scopus.subject | Compact model | |
fei.scopus.subject | Electrical characteristic | |
fei.scopus.subject | Model validation | |
fei.scopus.subject | MOSFETs | |
fei.scopus.subject | Nanowire transistors | |
fei.scopus.subject | Triple-gate | |
fei.scopus.subject | Wide temperature ranges | |
fei.scopus.updated | 2024-07-01 | |
fei.scopus.url | https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85050953816&origin=inward |