Analog performance of n-and p-FET SOI nanowires including channel length and temperature influence

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dc.contributor.authorPAZ, B. C.
dc.contributor.authorMarcelo Antonio Pavanello
dc.contributor.authorCASSE, M.
dc.contributor.authorBARRAUD, S.
dc.contributor.authorREIMBOLD, G.
dc.contributor.authorVINET, M.
dc.contributor.authorFAYNOT, O.
dc.contributor.authorOrcidhttps://orcid.org/0000-0003-1361-3650
dc.date.accessioned2022-01-12T21:59:03Z
dc.date.available2022-01-12T21:59:03Z
dc.date.issued2016-01-27
dc.description.abstractThis work aims to present the analog performance of silicon n-Type and p-MOSFET SOI nanowires. Analog parameters are shown at room temperature for both n-and p-Type, long and short channel devices with different channel width. Results for long channel n-MOS nanowires are investigated for the first time for low temperatures down to 100K. Moreover, an analysis is shown comparing the intrinsic voltage gain in nanowires and quasi-planar transistors. The mobility dependence on the temperature is found to be the key parameter to describe the behavior of both transconductance and output conductance when decreasing temperature.
dc.description.firstpage170
dc.description.lastpage173
dc.identifier.citationPAZ, B. C.; PAVANELLO, M. A.; CASSE, M.; BARRAUD, S.; REIMBOLD, G.; VINET, M.; FAYNOT, O. Analog performance of n-and p-FET SOI nanowires including channel length and temperature influence. 2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2016, p. 170-173, Jan. 2016.
dc.identifier.doi10.1109/ULIS.2016.7440080
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/3903
dc.relation.ispartof2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2016
dc.rightsAcesso Restrito
dc.subject.otherlanguageAnalog performance
dc.subject.otherlanguageLow temperature
dc.subject.otherlanguageMobility dependence
dc.subject.otherlanguageNanowires
dc.titleAnalog performance of n-and p-FET SOI nanowires including channel length and temperature influence
dc.typeArtigo de evento
fei.scopus.citations8
fei.scopus.eid2-s2.0-84966455394
fei.scopus.subjectAnalog parameters
fei.scopus.subjectAnalog performance
fei.scopus.subjectIntrinsic voltage gains
fei.scopus.subjectLow temperatures
fei.scopus.subjectOutput conductance
fei.scopus.subjectPlanar transistors
fei.scopus.subjectShort-channel devices
fei.scopus.subjectTemperature influence
fei.scopus.updated2024-07-01
fei.scopus.urlhttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84966455394&origin=inward
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