Modeling of silicon stacked nanowire and nanosheet transistors at high temperatures
| dc.contributor.author | CERDEIRA, A. | |
| dc.contributor.author | ESTRADA, M. | |
| dc.contributor.author | DA SILVA, G. M. | |
| dc.contributor.author | RODRIGUES, J. C. | |
| dc.contributor.author | Marcelo Antonio Pavanello | |
| dc.contributor.authorOrcid | https://orcid.org/0000-0003-1361-3650 | |
| dc.date.accessioned | 2022-12-01T06:03:23Z | |
| dc.date.available | 2022-12-01T06:03:23Z | |
| dc.date.issued | 2022-07-04 | |
| dc.description.abstract | © 2022 IEEE.In this work, we demonstrate that the Symmetric Doped Double-Gate Model (SDDGM), previously validated for modeling FinFETs, stacked nanowire, and nanosheet transistors at room temperature, can be extended for modeling stacked nanowire and nanosheet transistors at high temperatures. The modeled results are validated by comparison with experimental data. | |
| dc.identifier.citation | CERDEIRA, A.; ESTRADA, M.; DA SILVA, G. M.; RODRIGUES, J. C.; PAVANELLO, M. A. Modeling of silicon stacked nanowire and nanosheet transistors at high temperatures. 2022 IEEE Latin America Electron Devices Conference, LAEDC 2022, Jul. 2022. | |
| dc.identifier.doi | 10.1109/LAEDC54796.2022.9908193 | |
| dc.identifier.uri | https://repositorio.fei.edu.br/handle/FEI/4650 | |
| dc.relation.ispartof | 2022 IEEE Latin America Electron Devices Conference, LAEDC 2022 | |
| dc.rights | Acesso Restrito | |
| dc.subject.otherlanguage | compact modeling | |
| dc.subject.otherlanguage | high temperature | |
| dc.subject.otherlanguage | Si nanosheets | |
| dc.subject.otherlanguage | stacked transistors | |
| dc.title | Modeling of silicon stacked nanowire and nanosheet transistors at high temperatures | |
| dc.type | Artigo de evento | |
| fei.scopus.citations | 1 | |
| fei.scopus.eid | 2-s2.0-85141428912 | |
| fei.scopus.subject | Compact model | |
| fei.scopus.subject | Double-gate | |
| fei.scopus.subject | FinFETs | |
| fei.scopus.subject | Gate models | |
| fei.scopus.subject | Highest temperature | |
| fei.scopus.subject | Si nanosheet | |
| fei.scopus.subject | Stacked transistors | |
| fei.scopus.subject | Symmetrics | |
| fei.scopus.updated | 2025-02-01 | |
| fei.scopus.url | https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85141428912&origin=inward |