Mutually connected phase-locked loop networks: Dynamical models and design parameters

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dc.contributor.authorOrsatti F. M.
dc.contributor.authorCarareto R.
dc.contributor.authorPiqueira J. R. C.
dc.date.accessioned2022-01-12T22:04:50Z
dc.date.available2022-01-12T22:04:50Z
dc.date.issued2008
dc.description.abstractDistribution of timing signals is an essential factor for the development of digital systems for telecommunication networks, integrated circuits and manufacturing automation. Originally, this distribution was implemented by using the master-slave architecture with a precise master clock generator sending signals to phase-locked loops (PLL) working as slave oscillators. Nowadays, wireless networks with dynamical connectivity and the increase in size and operation frequency of the integrated circuits suggest that the distribution of clock signals could be more efficient if mutually connected architectures were used. Here, mutually connected PLL networks are studied and conditions for synchronous states existence are analytically derived, depending on individual node parameters and network connectivity, considering that the nodes are nonlinear oscillators with nonlinear coupling conditions. An expression for the network synchronisation frequency is obtained. The lock-in range and the transmission error bounds are analysed providing hints to the design of this kind of clock distribution system. © 2008 The Institution of Engineering and Technology.
dc.description.firstpage495
dc.description.issuenumber6
dc.description.lastpage508
dc.description.volume2
dc.identifier.citationORSATTI, F. M; CARARETO, R.; PIQUEIRA, J. R. C. Mutually connected phase-locked loop networks: Dynamical models and design parameters. IET Circuits, Devices and Systems, v. 2, n. 6, p. 495-508, 2008.
dc.identifier.doi10.1049/iet-cds:20080116
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/4298
dc.relation.ispartofIET Circuits, Devices and Systems
dc.rightsAcesso Restrito
dc.titleMutually connected phase-locked loop networks: Dynamical models and design parameters
dc.typeArtigo
fei.scopus.citations13
fei.scopus.eid2-s2.0-57349129293
fei.scopus.subjectClock distribution systems
fei.scopus.subjectClock signals
fei.scopus.subjectDesign Parameters
fei.scopus.subjectDigital systems
fei.scopus.subjectDynamical models
fei.scopus.subjectManufacturing automations
fei.scopus.subjectMaster clocks
fei.scopus.subjectNetwork connectivities
fei.scopus.subjectNode parameters
fei.scopus.subjectNonlinear couplings
fei.scopus.subjectNonlinear oscillators
fei.scopus.subjectOperation frequencies
fei.scopus.subjectSending signals
fei.scopus.subjectSynchronisation
fei.scopus.subjectSynchronous states
fei.scopus.subjectTiming signals
fei.scopus.subjectTransmission errors
fei.scopus.updated2024-11-01
fei.scopus.urlhttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=57349129293&origin=inward
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