Analytical compact model for triple gate junctionless MOSFETs

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dc.contributor.advisorOrcidhttps://orcid.org/0000-0003-1361-3650
dc.contributor.authorHERRERA, F. A.
dc.contributor.authorCERDEIRA, A.
dc.contributor.authorPAZ, B. C.
dc.contributor.authorESTRADA, M.
dc.contributor.authorMarcelo Antonio Pavanello
dc.date.accessioned2022-01-12T21:59:46Z
dc.date.available2022-01-12T21:59:46Z
dc.date.issued2015-10-13
dc.description.abstractA new compact analytical model for triple gate junctionless transistors JLT is presented considering the capacitances when the fin height is reduced. For its calculation, the capacitance is separated into gate and silicon height capacitance. On the modeling side, threshold voltage, drain current model and short channel effects are modeled considering the influence of variable fin height. Based on our previous developed analytical model for 2D devices, which neglects the fin height effects, a 3D analytical compact model was developed including short channel effects. The 3D model presented is useful for modeling silicon triple gate junctionless transistors. The model validation is done by simulations varying the fin height and channel length.
dc.identifier.citationhttps://orcid.org/0000-0003-1361-3650
dc.identifier.citationHERRERA, F. A.; CERDEIRA, A.; PAZ, B. C.; ESTRADA, M.; PAVANELLO, M. A. Analytical compact model for triple gate junctionless MOSFETs. SBMicro 2015 - 30th Symposium on Microelectronics Technology and Devices. Oct. 2015.
dc.identifier.doi10.1109/SBMicro.2015.7298147
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/3954
dc.relation.ispartofSBMicro 2015 - 30th Symposium on Microelectronics Technology and Devices
dc.rightsAcesso Restrito
dc.subject.otherlanguagecapacitances
dc.subject.otherlanguageJunctionless transistor
dc.subject.otherlanguageSCE
dc.titleAnalytical compact model for triple gate junctionless MOSFETs
dc.typeArtigo de evento
fei.scopus.citations1
fei.scopus.eid2-s2.0-84961774397
fei.scopus.subject3-d modeling
fei.scopus.subjectChannel length
fei.scopus.subjectCompact model
fei.scopus.subjectDrain current models
fei.scopus.subjectJunctionless transistors
fei.scopus.subjectModel validation
fei.scopus.subjectShort-channel effect
fei.scopus.subjectTriple-gate
fei.scopus.updated2024-07-01
fei.scopus.urlhttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84961774397&origin=inward
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