Impact of asymmetric channel configuration on the linearity of double-gate SOI MOSFETs
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7
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2006-04-26
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Marcelo Antonio Pavanello
CERDEIRA, A.
MARTINO, J. A.
RASKIN, J. P.
FLANDRE, D.
CERDEIRA, A.
MARTINO, J. A.
RASKIN, J. P.
FLANDRE, D.
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Proceedings of the Sixth International Caribbean Conference on Devices, Circuits and Systems, ICCDCS 2006 - Final Program and Technical Digest
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PAVANELLO, M. A.; CERDEIRA, A.; MARTINO, J. A.; RASKIN, J. P.; FLANDRE, D. Impact of asymmetric channel configuration on the linearity of double-gate SOI MOSFETs. Proceedings of the Sixth International Caribbean Conference on Devices, Circuits and Systems, ICCDCS 2006 - Final Program and Technical Digest, p. 187-194, 2006
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In this paper the linearity of asymmetric channel double-gate transistors, using the graded-channel (GC) configuration and Gate-All-Around architecture, operating as an amplifier, is studied in terms of lightly doped region length. The total harmonic distortion and third-order harmonic distortion are used as figures of merit. The results are compared with single-gate transistors with similar channel configuration. It is demonstrated that double-gate GC transistors at the same operation region and with similar channel configuration can present up to 20 dB less total harmonic distortion while presenting small third-order harmonic distortion. Considering similar bias voltage, the alternate component of the input sinusoidal signal of GC double-gate devices can be increased by about 200 mV to provide similar third-order harmonic distortion maintaining similar improvements of 20 dB on the total harmonic distortion. © 2006 IEEE.