Application of double gate graded-channel SOI in MOSFET-C balanced structures
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Data
2007-05-11
Autores
Rodrigo Doria
Marcelo Antonio Pavanello
CERDEIRA, A.
RASKIN J. P.
FLANDRE, D.
Marcelo Antonio Pavanello
CERDEIRA, A.
RASKIN J. P.
FLANDRE, D.
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Periódico
ECS Transactions
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DORIA, R.; PAVANELLO, M. A.; CERDEIRA, A.; RASKIN J. P.; FLANDRE, D. Application of double gate graded-channel SOI in MOSFET-C balanced structures. ECS Transactions, v. 6, n. 4, p. 217-222, May, 2007.
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This work studies the linearity of conventional and Graded-Channel (GC) Gate-All-Around (GAA) devices when applied in 2-MOS and 4-MOS balanced structures operating as tunable resistors. The study has been performed through device characterization and two-dimensional process and device simulations. Total harmonic distortion (THD) and third order harmonic distortion (HD3) have been evaluated. When taking into account similar on-resistance, the use of the GC GAA transistors in both 2-MOS and 4-MOS structures improves the linearity. The use of GC GAA devices in 2-MOS balanced structures allows a reduction of the gate overdrive voltage of 22.5% without degrading THD and HD3. On the other hand, the use of GC GAA devices in 4-MOS structures leads to an improvement in both HD3 and THD by 7 dB for devices with similar channel length at the same gate voltage overdrive. © The Electrochemical Society.