Application of double gate graded-channel SOI in MOSFET-C balanced structures
dc.contributor.author | Rodrigo Doria | |
dc.contributor.author | Marcelo Antonio Pavanello | |
dc.contributor.author | CERDEIRA, A. | |
dc.contributor.author | RASKIN J. P. | |
dc.contributor.author | FLANDRE, D. | |
dc.contributor.authorOrcid | https://orcid.org/0000-0003-1361-3650 | |
dc.contributor.authorOrcid | https://orcid.org/0000-0003-4448-4337 | |
dc.date.accessioned | 2022-01-12T22:05:16Z | |
dc.date.available | 2022-01-12T22:05:16Z | |
dc.date.issued | 2007-05-11 | |
dc.description.abstract | This work studies the linearity of conventional and Graded-Channel (GC) Gate-All-Around (GAA) devices when applied in 2-MOS and 4-MOS balanced structures operating as tunable resistors. The study has been performed through device characterization and two-dimensional process and device simulations. Total harmonic distortion (THD) and third order harmonic distortion (HD3) have been evaluated. When taking into account similar on-resistance, the use of the GC GAA transistors in both 2-MOS and 4-MOS structures improves the linearity. The use of GC GAA devices in 2-MOS balanced structures allows a reduction of the gate overdrive voltage of 22.5% without degrading THD and HD3. On the other hand, the use of GC GAA devices in 4-MOS structures leads to an improvement in both HD3 and THD by 7 dB for devices with similar channel length at the same gate voltage overdrive. © The Electrochemical Society. | |
dc.description.firstpage | 217 | |
dc.description.issuenumber | 4 | |
dc.description.lastpage | 222 | |
dc.description.volume | 6 | |
dc.identifier.citation | DORIA, R.; PAVANELLO, M. A.; CERDEIRA, A.; RASKIN J. P.; FLANDRE, D. Application of double gate graded-channel SOI in MOSFET-C balanced structures. ECS Transactions, v. 6, n. 4, p. 217-222, May, 2007. | |
dc.identifier.doi | 10.1149/1.2728864 | |
dc.identifier.issn | 1938-5862 | |
dc.identifier.uri | https://repositorio.fei.edu.br/handle/FEI/4327 | |
dc.relation.ispartof | ECS Transactions | |
dc.rights | Acesso Restrito | |
dc.title | Application of double gate graded-channel SOI in MOSFET-C balanced structures | |
dc.type | Artigo de evento | |
fei.scopus.citations | 1 | |
fei.scopus.eid | 2-s2.0-45249116595 | |
fei.scopus.subject | (e ,3e) process | |
fei.scopus.subject | Applied (CO) | |
fei.scopus.subject | Balanced structures | |
fei.scopus.subject | channel lengths | |
fei.scopus.subject | Device characterization | |
fei.scopus.subject | Device simulations | |
fei.scopus.subject | Distortion (deformation) | |
fei.scopus.subject | Double gate (DG) | |
fei.scopus.subject | Electrochemical Society (ECS) | |
fei.scopus.subject | GAA devices | |
fei.scopus.subject | Gate voltages | |
fei.scopus.subject | Gate-all-around (GAA) devices | |
fei.scopus.subject | International symposium | |
fei.scopus.subject | Metal oxide semiconductor (MOS) structures | |
fei.scopus.subject | On-resistance (Rons) | |
fei.scopus.subject | Silicon on insulator (SOI) technology | |
fei.scopus.subject | Third-order | |
fei.scopus.subject | Total Harmonic Distortion (TDH) | |
fei.scopus.subject | Tunable resistors | |
fei.scopus.subject | Two-dimensional (2D) | |
fei.scopus.updated | 2025-02-01 | |
fei.scopus.url | https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=45249116595&origin=inward |