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Application of double gate graded-channel SOI in MOSFET-C balanced structures

dc.contributor.authorRodrigo Doria
dc.contributor.authorMarcelo Antonio Pavanello
dc.contributor.authorCERDEIRA, A.
dc.contributor.authorRASKIN J. P.
dc.contributor.authorFLANDRE, D.
dc.contributor.authorOrcidhttps://orcid.org/0000-0003-1361-3650
dc.contributor.authorOrcidhttps://orcid.org/0000-0003-4448-4337
dc.date.accessioned2022-01-12T22:05:16Z
dc.date.available2022-01-12T22:05:16Z
dc.date.issued2007-05-11
dc.description.abstractThis work studies the linearity of conventional and Graded-Channel (GC) Gate-All-Around (GAA) devices when applied in 2-MOS and 4-MOS balanced structures operating as tunable resistors. The study has been performed through device characterization and two-dimensional process and device simulations. Total harmonic distortion (THD) and third order harmonic distortion (HD3) have been evaluated. When taking into account similar on-resistance, the use of the GC GAA transistors in both 2-MOS and 4-MOS structures improves the linearity. The use of GC GAA devices in 2-MOS balanced structures allows a reduction of the gate overdrive voltage of 22.5% without degrading THD and HD3. On the other hand, the use of GC GAA devices in 4-MOS structures leads to an improvement in both HD3 and THD by 7 dB for devices with similar channel length at the same gate voltage overdrive. © The Electrochemical Society.
dc.description.firstpage217
dc.description.issuenumber4
dc.description.lastpage222
dc.description.volume6
dc.identifier.citationDORIA, R.; PAVANELLO, M. A.; CERDEIRA, A.; RASKIN J. P.; FLANDRE, D. Application of double gate graded-channel SOI in MOSFET-C balanced structures. ECS Transactions, v. 6, n. 4, p. 217-222, May, 2007.
dc.identifier.doi10.1149/1.2728864
dc.identifier.issn1938-5862
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/4327
dc.relation.ispartofECS Transactions
dc.rightsAcesso Restrito
dc.titleApplication of double gate graded-channel SOI in MOSFET-C balanced structures
dc.typeArtigo de evento
fei.scopus.citations1
fei.scopus.eid2-s2.0-45249116595
fei.scopus.subject(e ,3e) process
fei.scopus.subjectApplied (CO)
fei.scopus.subjectBalanced structures
fei.scopus.subjectchannel lengths
fei.scopus.subjectDevice characterization
fei.scopus.subjectDevice simulations
fei.scopus.subjectDistortion (deformation)
fei.scopus.subjectDouble gate (DG)
fei.scopus.subjectElectrochemical Society (ECS)
fei.scopus.subjectGAA devices
fei.scopus.subjectGate voltages
fei.scopus.subjectGate-all-around (GAA) devices
fei.scopus.subjectInternational symposium
fei.scopus.subjectMetal oxide semiconductor (MOS) structures
fei.scopus.subjectOn-resistance (Rons)
fei.scopus.subjectSilicon on insulator (SOI) technology
fei.scopus.subjectThird-order
fei.scopus.subjectTotal Harmonic Distortion (TDH)
fei.scopus.subjectTunable resistors
fei.scopus.subjectTwo-dimensional (2D)
fei.scopus.updated2025-02-01
fei.scopus.urlhttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=45249116595&origin=inward

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