Electrical characteristics of n-type vertically stacked nanowires operating up to 600 K
dc.contributor.author | MARINIELLO, G. | |
dc.contributor.author | BARRAUD, S. | |
dc.contributor.author | VINET, M. | |
dc.contributor.author | CASSE, M. | |
dc.contributor.author | FAYNOT, O. | |
dc.contributor.author | CALCADE, J. | |
dc.contributor.author | Marcelo Antonio Pavanello | |
dc.contributor.authorOrcid | https://orcid.org/0000-0003-1361-3650 | |
dc.contributor.authorOrcid | https://orcid.org/0000-0003-1361-3650 | |
dc.date.accessioned | 2022-06-01T06:04:55Z | |
dc.date.available | 2022-06-01T06:04:55Z | |
dc.date.issued | 2022-08-05 | |
dc.description.abstract | © 2022 Elsevier LtdThis paper aims at analyzing the electrical characteristics of n-type vertically stacked nanowires with variable fin width, operating in the temperature range of 300–600 K. Basic electrical parameters, such as threshold voltage, subthreshold slope, and carrier mobility are extracted in the linear region, whereas the transconductance, output conductance, and intrinsic voltage gain are extracted in saturation, to access some of device's analog figures of merit. Also, it has been analyzed the DIBL, GIDL, Ion, and Ioff. currents. | |
dc.description.volume | 194 | |
dc.identifier.citation | MARINIELLO, G.; BARRAUD, S.; VINET, M.; CASSE, M.; FAYNOT, O.; CALCADE, J.; PAVANELLO, M. A. Electrical characteristics of n-type vertically stacked nanowires operating up to 600 K. Solid-State Electronics, v. 194, August, 2022. | |
dc.identifier.doi | 10.1016/j.sse.2022.108337 | |
dc.identifier.issn | 0038-1101 | |
dc.identifier.uri | https://repositorio.fei.edu.br/handle/FEI/4499 | |
dc.relation.ispartof | Solid-State Electronics | |
dc.rights | Acesso Restrito | |
dc.subject.otherlanguage | DIBL | |
dc.subject.otherlanguage | High temperature | |
dc.subject.otherlanguage | Vertically stacked nanowires | |
dc.title | Electrical characteristics of n-type vertically stacked nanowires operating up to 600 K | |
dc.type | Artigo | |
fei.scopus.citations | 5 | |
fei.scopus.eid | 2-s2.0-85130227820 | |
fei.scopus.subject | DIBL | |
fei.scopus.subject | Electrical characteristic | |
fei.scopus.subject | Electrical parameter | |
fei.scopus.subject | Fin widths | |
fei.scopus.subject | Highest temperature | |
fei.scopus.subject | Linear region | |
fei.scopus.subject | Output conductance | |
fei.scopus.subject | Subthreshold slope | |
fei.scopus.subject | Temperature range | |
fei.scopus.subject | Vertically stacked nanowire | |
fei.scopus.updated | 2025-02-01 | |
fei.scopus.url | https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85130227820&origin=inward |