The wave SOI MOSFET: A new accuracy transistor layout to improve drain current and reduce die area for current drivers applications
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17
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Data
2009-05-29
Autores
Salvador Gimenez
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Periódico
ECS Transactions
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GIMENEZ, S. The wave SOI MOSFET: A new accuracy transistor layout to improve drain current and reduce die area for current drivers applications. ECS Transactions, v. 19, n. 4, p. 153-158, Mayo 2009.
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This paper proposes a new transistor layout, called here simply as Wave, that can be used for any technology, to improve the current driver and enhanced layout packing with respect to Multifinger and Waffle structures, regarding the same geometric factor Discussions about this novel layout approach are performed regarding matching, avalanche and electro static discharge. To verify the benefits of the Wave structure, a comparison with a Multifinger and Waffle is carried out. Defining a figure-of-merit as integration factor [(W/L)/A], the Wave features a better efficiency than Multifinger and Waffle layouts, as 35.9 % and 28.1% respectively. The Wave approach allows a saving of 26.1 % and 21.8% in the power SOI MOSFET size as compared to Multifinger and Waffle layouts. ©The Electrochemical Society.