Customized Imperialist Competitive Algorithm Methodology to Optimize Robust Miller CMOS OTAs

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dc.contributor.authorGALEMBECK, E. H. S.
dc.contributor.authorSalvador Gimenez
dc.contributor.authorMORETO, R. A. D. L.
dc.contributor.authorOrcidhttps://orcid.org/0000-0002-3616-9559
dc.date.accessioned2023-01-01T06:02:42Z
dc.date.available2023-01-01T06:02:42Z
dc.date.issued2022
dc.description.abstract© 2022 by the authors.The design and optimization of the analog complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) are intrinsically complicated and depend heavily on the designer’s experience, and are associated with very long design and optimization-cycle times. In addition, in order to the analog and radiofrequency (RF) CMOS IC work suitably in practice, it is necessary to perform robustness analyses (RAs) through Simulation Program with Integrated Circuit Emphasis (SPICE) simulations, which result in still-higher design and optimization cycle times and therefore represent the biggest bottleneck to the launching of new electronic products. In this context, this manuscript aims to present, for the first time, the use of a custom imperialist competitive algorithm (ICA) in order to reduce the design and optimization-cycle times of analog CMOS ICs. In this study, we implement some Miller CMOS operational transconductance amplifiers (OTAs) using the computational tool named iMTGSPICE, considering two different bulk CMOS IC manufacturing processes from Taiwan Semiconductor Company (TSMC) (180 nm and 65 nm nodes) and two evolutionary optimization methodologies of artificial intelligence, i.e., ICA and a genetic algorithm (GA). The main result obtained by this work shows that, by using an ICA-customized evolutionary algorithm to perform the design and optimization processes of Miller CMOS OTAs, it is possible to reduce the design and optimization-cycle times by up to 83% in relation to those implemented with the GA-customized evolutionary algorithm, achieving practically the same electrical performance.
dc.description.issuenumber23
dc.description.volume11
dc.identifier.citationGALEMBECK, E. H. S.; GIMENEZ, S.; MORETO, R. A. D. L. Customized Imperialist Competitive Algorithm Methodology to Optimize Robust Miller CMOS OTAs. Electronics (Switzerland), v.11, v. 23, nov. 2022.
dc.identifier.doi10.3390/electronics11233923
dc.identifier.issn2079-9292
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/4667
dc.relation.ispartofElectronics (Switzerland)
dc.rightsAcesso Aberto
dc.rights.licenseCreative Commons "Este é um artigo publicado em acesso aberto sob uma licença Creative commons (CC BY 4.0). Fonte: https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85143727090&origin=inward. Acesso em 05 jan. 2023.
dc.subject.otherlanguageanalog CMOS IC design
dc.subject.otherlanguagegenetic algorithm
dc.subject.otherlanguageimperialist competitive algorithm
dc.subject.otherlanguageMiller CMOS OTA
dc.subject.otherlanguagerobustness analyses
dc.titleCustomized Imperialist Competitive Algorithm Methodology to Optimize Robust Miller CMOS OTAs
dc.typeArtigo
fei.scopus.citations1
fei.scopus.eid2-s2.0-85143727090
fei.scopus.updated2024-07-01
fei.scopus.urlhttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85143727090&origin=inward
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