Surface Potential-Based Drain Current Analytical Model for Triple-Gate Junctionless Nanowire Transistors

Página do item simplificado
dc.contributor.authorTREVISOLI, R D
dc.contributor.authorDORIA, R. T.
dc.contributor.authorDE SOUZA, Michelly
dc.contributor.authorDAS, Samaresh
dc.contributor.authorFERAIN, I.
dc.contributor.authorPAVANELLO, Marcelo A.
dc.date.accessioned2019-08-19T23:45:10Z
dc.date.available2019-08-19T23:45:10Z
dc.date.issued2012
dc.description.firstpage3510
dc.description.issuenumber12
dc.description.lastpage3518
dc.description.volume59
dc.identifier.citationTREVISOLI, R D; DORIA, R. T.; DE SOUZA, Michelly; DAS, Samaresh; FERAIN, I.; PAVANELLO, Marcelo A.. Surface Potential-Based Drain Current Analytical Model for Triple-Gate Junctionless Nanowire Transistors. IEEE Transactions on Electron Devices, v. 59, n. 12, p. 3510-3518, 2012.
dc.identifier.doi10.1109/TEd.2012.2219055
dc.identifier.issn0018-9383
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/1097
dc.relation.ispartofIEEE Transactions on Electron Devices
dc.rightsAcesso Restrito
dc.titleSurface Potential-Based Drain Current Analytical Model for Triple-Gate Junctionless Nanowire Transistorspt_BR
dc.typeArtigopt_BR
fei.scopus.citations93
fei.scopus.eid2-s2.0-84870302975
fei.scopus.updated2023-12-01
Arquivos
Coleções
Artigos