Analysis of the scattering mechanisms in the accumulation layer of junctionless nanowire transistors at high temperature
dc.contributor.advisorOrcid | https://orcid.org/0000-0003-1361-3650 | |
dc.contributor.author | RIBEIRO, T. A. | |
dc.contributor.author | Marcelo Antonio Pavanello | |
dc.date.accessioned | 2023-06-01T06:23:58Z | |
dc.date.available | 2023-06-01T06:23:58Z | |
dc.date.issued | 2019-08-05 | |
dc.description.abstract | © 2019 IEEE.This work studies the effects of high temperature on the scattering mechanisms of Junctionless Nanowire Transistors with several fin width from nanowire to quasi-planar devices. With the variation of the temperature it was possible to analyze the impact of the scattering mechanisms on the devices. For nanowire devices at room temperature a degradation of up to 19% was seen from the maximum mobility to the mobility at higher gate bias to around 15% at 500K, while quasi-planar devices show a degradation of around 12% for all temperatures. Further analysis shows that the impact of the surface roughness for nanowires increase the degradation of these devices, where a reduction of its degradation at higher temperature shows the phonon scattering as the main scattering mechanism. | |
dc.identifier.citation | RIBEIRO, T. A.; PAVANELLO, M. A. Analysis of the scattering mechanisms in the accumulation layer of junctionless nanowire transistors at high temperature. SBMicro 2019 - 34th Symposium on Microelectronics Technology and Devices, aug. 2019. | |
dc.identifier.doi | 10.1109/SBMicro.2019.8919428 | |
dc.identifier.uri | https://repositorio.fei.edu.br/handle/FEI/4827 | |
dc.relation.ispartof | SBMicro 2019 - 34th Symposium on Microelectronics Technology and Devices | |
dc.rights | Acesso Restrito | |
dc.subject.otherlanguage | Electric Field | |
dc.subject.otherlanguage | Electron Mobility | |
dc.subject.otherlanguage | Juntionless | |
dc.subject.otherlanguage | Nanowire | |
dc.subject.otherlanguage | Scattering Mechanisms | |
dc.title | Analysis of the scattering mechanisms in the accumulation layer of junctionless nanowire transistors at high temperature | |
dc.type | Artigo de evento | |
fei.scopus.citations | 1 | |
fei.scopus.eid | 2-s2.0-85077183234 | |
fei.scopus.subject | Accumulation layers | |
fei.scopus.subject | High temperature | |
fei.scopus.subject | Juntionless | |
fei.scopus.subject | Nanowire devices | |
fei.scopus.subject | Nanowire transistors | |
fei.scopus.subject | Planar devices | |
fei.scopus.subject | Scattering mechanisms | |
fei.scopus.subject | Work study | |
fei.scopus.updated | 2025-02-01 | |
fei.scopus.url | https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85077183234&origin=inward |