Synthesis of low-power synchronous digital systems operating in double-edge of the clock

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dc.contributor.authorOLIVEIRA, D. L.
dc.contributor.authorCURTINHA, T.
dc.contributor.authorFARIA, L.
dc.contributor.authorROMANO, L.
dc.date.accessioned2022-01-12T22:02:09Z
dc.date.available2022-01-12T22:02:09Z
dc.date.issued2012-11-09
dc.description.abstractIn a synchronous digital system, the activity of the clock signal is a major energy consumer. It is responsible for 15% to 45% of the total consumed energy. Once reducing the activity of the clock signal, it is possible not only a reduction of the considered energy, but also a reduction of clock skew problems and electromagnetic iteration. An interesting strategy to achieve this goal is to design the synchronous digital system to operate in transitions of both edges of the clock signal (double-edge triggered - DET), once it allows a 50% reduction in the frequency of the clock signal, although showing the same processing rate data. In this paper it is proposed a method that synthesizes synchronous digital systems that operate on both edges of the clock signal, using only flip-flops sensitive to a single edge of the clock signal (single-edge triggered flip-flops - SET-FF) as components of the state memory. The proposed method presents good results and a high probability of practical implementation. © 2012 IEEE.
dc.description.firstpage59
dc.description.lastpage62
dc.identifier.citationOLIVEIRA, D. L.; CURTINHA, T.; FARIA, L.; ROMANO, L. Synthesis of low-power synchronous digital systems operating in double-edge of the clock. Proceedings of the 6th Andean Region International Conference, Andescon, p. 59-62, 2012.
dc.identifier.doi10.1109/Andescon.2012.23
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/4115
dc.relation.ispartofProceedings of the 6th Andean Region International Conference, Andescon 2012
dc.rightsAcesso Restrito
dc.subject.otherlanguagedouble-edge clock
dc.subject.otherlanguagelow-power
dc.subject.otherlanguagepartitioning
dc.subject.otherlanguageSET-FFs
dc.subject.otherlanguagestate assignment
dc.titleSynthesis of low-power synchronous digital systems operating in double-edge of the clock
dc.typeArtigo de evento
fei.scopus.citations0
fei.scopus.eid2-s2.0-84880726985
fei.scopus.subjectConsumed energy
fei.scopus.subjectEnergy consumer
fei.scopus.subjectHigh probability
fei.scopus.subjectLow Power
fei.scopus.subjectpartitioning
fei.scopus.subjectProcessing rates
fei.scopus.subjectSET-FFs
fei.scopus.subjectSynchronous digital system
fei.scopus.updated2024-07-01
fei.scopus.urlhttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84880726985&origin=inward
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