Artigos
URI permanente para esta coleçãohttps://repositorio.fei.edu.br/handle/FEI/798
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- Different stress techniques and their efficiency on triple-gate SOI n-MOSFETs(2015) Buhler R.T.; Agopian P.G.D.; Collaert N.; Simoen E.; Claeys C.; Martino J.A.© 2014 Elsevier Ltd. All rights reserved.Three techniques to implement mechanical stress in n-channel Multiple Gate MOSFETs (MuGFETs) are investigated through 3D simulations and transconductance measurements. They are: uniaxial stress, biaxial stress and biaxial + uniaxial stress. Four different fin dimensions are evaluated: a narrow and a wide transistor, combined with a short or a long device. It is shown that the stress distribution and the device performance exhibit a dependence on the fin dimensions. For uniaxially strained devices, the dimensions are important as the bending of the silicon required to induce stress in the channel depends on its size. However, for biaxially strained devices the plane of etching in the silicon fin is important, determining the degradation of the stress components. The combination of the two types of stress results in an improvement of some stress components and an overall improvement in the maximum transconductance.
- An analytic method to compute the stress dependence on the dimensions and its influence in the characteristics of triple gate devices(2012) Trevisoli R.D.; Martino J.A.; Simoen E.; Claeys C.; Pavanello M.A.Triple-gate devices are considered a promising solution for sub-20 nm era. Strain engineering has also been recognized as an alternative due to the increase in the carriers mobility it propitiates. The simulation of strained devices has the major drawback of the stress non-uniformity, which cannot be easily considered in a device TCAD simulation without the coupled process simulation that is time consuming and cumbersome task. However, it is mandatory to have accurate device simulation, with good correlation with experimental results of strained devices, allowing for in-depth physical insight as well as prediction on the stress impact on the device electrical characteristics. This work proposes the use of an analytic function, based on the literature, to describe accurately the strain dependence on both channel length and fin width in order to simulate adequately strained triple-gate devices. The maximum transconductance and the threshold voltage are used as the key parameters to compare simulated and experimental data. The results show the agreement of the proposed analytic function with the experimental results. Also, an analysis on the threshold voltage variation is carried out, showing that the stress affects the dependence of the threshold voltage on the temperature. © 2011 Elsevier Ltd. All rights reserved.
- Analysis of temperature variation influence on the analog performance of 45° rotated triple-gate nMuGFETs(2012) Pavanello M.A.; Souza M.D.; Martino J.A.; Simoen E.; Claeys C.This work presents the analog performance of n-type triple-gate MuGFETs with high-k dielectrics and TiN gate material fabricated in 45° rotated SOI substrates comparing their performance with standard MuGFETs fabricated without substrate rotation. Different fin widths are studied for temperatures ranging from 250 K up to 400 K. The results of transconductance, output conductance, transconductance over drain current ratio, intrinsic voltage gain and unit-gain frequency are studied. It is observed that the substrate rotation improves the carrier mobility of narrow MuGFETs at any temperature because of the changing in the conduction plane at the sidewalls from (1 1 0) to (1 0 0). For lower temperatures, the improvement of the carrier mobility of rotated MuGFETs is more noticeable as well as the rate of mobility improvement with the temperature decrease is larger. The output conductance is weakly affected by the substrate rotation. Although this improvement in the transconductance of rotated MuGFETs is negligibly transferred to the intrinsic voltage gain, the unity-gain frequency of rotated device is improved due to the larger carrier mobility in the entire range of temperatures studied. © 2011 Elsevier Ltd. All rights reserved.
- Analog performance of standard and strained triple-gate silicon-on-insulator nFinFETs(2008) Pavanello M.A.; Martino J.A.; Simoen E.; Rooyackers R.; Collaert N.; Claeys C.This work shows a comparison between the analog performance of standard and strained Si n-type triple-gate FinFETs with high-κ dielectrics and TiN gate material. Different channel lengths and fin widths are studied. It is demonstrated that both standard and strained FinFETs with short channel length and narrow fins have similar analog properties, whereas the increase of the channel length degrades the early voltage of the strained devices, consequently decreasing the device intrinsic voltage gain with respect to standard ones. Narrow strained FinFETs with long channel show a degradation of the Early voltage if compared to standard ones suggesting that strained devices are more subjected to the channel length modulation effect. © 2008 Elsevier Ltd. All rights reserved.