Artigos
URI permanente para esta coleçãohttps://repositorio.fei.edu.br/handle/FEI/798
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19 resultados
Resultados da Pesquisa
- Threshold voltages of SOI MuGFETs(2008-12-05) de Andrade M.G.C.; Martino J.A.The multiple-gate field-effect transistor (MuGFET) is a device with a gate folded on different sides of the channel region. They are one of the most promising technological solutions to create high-performance ultra-scaled SOI CMOS. In this work, the behavior of the threshold voltage in double-gate, triple-gate and quadruple-gate SOI transistors with different channel doping concentrations is studied through three-dimensional numerical simulation. The results indicated that for double-gate transistors, one or two threshold voltages can be observed, depending on the channel doping concentration. However, in triple-gate and quadruple-gate it is possible to observe up to four threshold voltages due to the corner effect and the different doping concentration between the top and bottom of the Fin. © 2008 Elsevier Ltd. All rights reserved.
- Halo optimization for 0.13μm SOI CMOS technology(2008) Agopian P.G.D.; Arrabaca J.M.; Martino J.A.This work presents the study of HALO implantation angle and its concentration influence on deep-submicrometer partially depleted SOI nMOSFETs electric characteristics. This study was performed through the threshold voltage and subthreshold slope analysis. As the implantation angle and the doping concentration of the HALO were varied, a large threshold voltage variation was obtained. It is demonstrated that for 0.13μm SOI CMOS technology devices, the most efficient HALO implantation occurs for 50 degrees and concentration range from 1.2×1018 cm-3 to 1.8×10 18cm-33. © The Electrochemical Society.
- SOI technology characterization using SOI-MOS capacitor(2005) Sonnenberg V.; Martino J.A.In this paper a set of simple methods is presented, to determine the main parameters of the silicon on insulator technology, using a thin film SOI-MOS capacitor. Methods to obtain the effective substrate doping concentration, substrate interface charge density and the buried oxide thickness using the two terminal SOI capacitor are presented. The front gate oxide thickness, the silicon film thickness, the silicon doping concentration and front and back interface charge density are obtained using a three terminal SOI-MOS capacitor. Bidimensional numerical simulations of SOI structure are performed for analyzing the high frequency capacitance vs. voltage curves and to test the proposed methods. These methods were applied experimentally and coherent results were found. © 2004 Elsevier Ltd. All rights reserved.
- Modeling silicon on insulator MOS transistors with nonrectangular-gate layouts(2006) Giacomini R.; Martino J.A.This work presents a new and simple approach for modeling silicon on insulator metal-oxide-semiconductor (MOS) dc characteristics for nonrectangular layout devices, based on decomposition of the original shape into trapezoidal parts and on an accurate but simple model of the trapezoidal layout transistor. Analytical expressions relating geometrical parameters and terminal current and voltages are presented for several shapes, such as L, U, T, and S, and other well-known devices such as the edgeless transistor and the asymmetric trapezoidal gate transistor. The proposed closed-form analytical expressions show good agreement with measured data and three-dimensional simulation results. © 2006 The Electrochemical Society. All rights reserved.
- Trapezoidal cross-sectional influence on FinFET threshold voltage and corner effects(2008) Giacomini R.; Martino J.A.Fin field effect transistors (FinFETS) are silicon-on-insulator (SOI) transistors with three-dimensional structures. As a result of some fabrication-process limitations (as nonideal anisotropic overetch) some FinFETs have inclined surfaces, which results in trapezoidal cross sections instead of rectangular sections, as expected. This geometric alteration results in some device issues, like carrier profile, threshold voltage, and corner effects. This work analyzes these consequences based on three-dimensional numeric simulation of several dual-gate and triple-gate FinFETs. The simulation results show that the threshold voltage depends on the sidewall inclination angle and that this dependence varies according to the body doping level. The corner effects also depend on the inclination angle and doping level. © 2008 The Electrochemical Society.
- A simple current model for edgeless SOI nMOSFET and a 3-D analysis(2005) Giacomini R.; Martino J.A.This work presents a new approach for the current model of thin-film, fully depleted SOI edgeless transistors, based on the asymmetric trapezoidal gate model. The most common current model for an edgeless transistor is obtained by taking the rectangular device drain current expression and substituting the device width by an "equivalent" device width, usually given by the average between source and drain width of the channel. However, this model does not take into account some effects that take place near the corners of the device and that have a significant influence on the current expression. The new model is tested using three-dimensional numerical simulation and experimental data. The proposed model is still simple and both simulation and experimental results show that it presents an improved performance. © 2005 Elsevier Ltd. All rights reserved.
- Low temperature influence on the uniaxially strained FD SOI nMOSFETs behavior(2007) de Souza M.; Pavanello M.A.; Martino J.A.; Simoen E.; Claeys C.This work presents the impact of low temperature operation on the characteristics of uniaxially strained fully-depleted SOI nMOSFETs. Devices with channel lengths down to 160 nm were explored in the range 100-380 K. The maximum transconductance in linear region was used to evaluate the mobility enhancement. Besides the increased mobility provided by the strain in comparison to its unstrained SOI counterpart, higher mobility degradation for high values of applied gate voltage was observed. The subthreshold slope and the Drain Induced Barrier Lowering (DIBL) of short-channel devices have been also analyzed, showing that strained devices are more susceptible to the occurrence of short-channel effects. © 2007 Elsevier B.V. All rights reserved.
- Analog performance of standard and strained triple-gate silicon-on-insulator nFinFETs(2008) Pavanello M.A.; Martino J.A.; Simoen E.; Rooyackers R.; Collaert N.; Claeys C.This work shows a comparison between the analog performance of standard and strained Si n-type triple-gate FinFETs with high-κ dielectrics and TiN gate material. Different channel lengths and fin widths are studied. It is demonstrated that both standard and strained FinFETs with short channel length and narrow fins have similar analog properties, whereas the increase of the channel length degrades the early voltage of the strained devices, consequently decreasing the device intrinsic voltage gain with respect to standard ones. Narrow strained FinFETs with long channel show a degradation of the Early voltage if compared to standard ones suggesting that strained devices are more subjected to the channel length modulation effect. © 2008 Elsevier Ltd. All rights reserved.
- Trapezoidal SOI FinFET analog parameters' dependence on cross-section shape(2009) Buhler R.T.; Giacomini R.; Pavanello M.A.; Martino J.A.The trapezium is often a better approximation for the FinFET cross-section shape, rather than the design-intended rectangle. The frequent width variations along the vertical direction, caused by the etching process that is used for fin definition, may imply in inclined sidewalls and the inclination angles can vary in a significant range. These geometric variations may cause some important changes in the device electrical characteristics. This work analyzes the influence of the FinFET sidewall inclination angle on some relevant parameters for analog design, such as threshold voltage, output conductance, transconductance, intrinsic voltage gain (AV), gate capacitance and unit-gain frequency, through 3D numeric simulation. The intrinsic gain is affected by alterations in transconductance and output conductance. The results show that both parameters depend on the shape, but in different ways. Transconductance depends mainly on the sidewall inclination angle and the fixed average fin width, whereas the output conductance depends mainly on the average fin width and is weakly dependent on the sidewall inclination angle. The simulation results also show that higher voltage gains are obtained for smaller average fin widths with inclination angles that correspond to inverted trapeziums, i.e. for shapes where the channel width is larger at the top than at the transistor base because of the higher attained transconductance. When the channel top is thinner than the base, the transconductance degradation affects the intrinsic voltage gain. The total gate capacitances also present behavior dependent on the sidewall angle, with higher values for inverted trapezium shapes and, as a consequence, lower unit-gain frequencies. © 2009 IOP Publishing Ltd.
- Cryogenic operation of FinFETs aiming at analog applications(2009) Pavanello M.A.; Martino J.A.; Simoen E.; Claeys C.FinFETs are recognized as promising candidates for the CMOS nanometer era. In this paper the most recent results for cryogenic operation of FinFETs will be demonstrated with special emphasis on analog applications. Threshold voltage, subthreshold slope and carrier mobility will be studied. Also some important figures of merit for analog circuit operation as for readout electronics, such as transconductance, output conductance and intrinsic voltage gain will be covered. It is demonstrated that the threshold voltage of undoped narrow FinFETs is less temperature-dependent than for a planar single-gate device with similar doping concentration. The temperature reduction improves the transconductance over drain current ratio in any operational region. On the other hand, the output conductance is degraded when the temperature is reduced. The combination of these effects shows that the intrinsic gain of a L = 90 nm FinFET is degraded by 2 dB when the temperature reduces from 300 K to 100 K. © 2009 Elsevier Ltd. All rights reserved.