Artigos
URI permanente para esta coleçãohttps://repositorio.fei.edu.br/handle/FEI/798
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- The role of the incomplete ionization on the operation of Junctionless Nanowire Transistors(2012-10-04) TREVISOLI, R. D.; Rodrido Doria; Michelly De Souza; FERAIN, I.; DAS, S.; Pavanello M.A.The use of planar MOS devices for the sub-20 nm era has become a great challenge due to the loss of the gate control on the channel charges [1]. Multi-gate architecture provides a better electrostatic control, allowing a higher degree of miniaturization [1]. One of the major drawbacks of either planar or multi-gate extremely short devices is the formation of p-n junctions between source/drain and the channel, which requires precise thermal conditions in order to avoid the impurities diffusion into the channel. In this context, Junctionless Nanowire Transistors (JNTs) have been developed [2-3]. They consist of heavy doped silicon nanowires (N+ for nMOS and P+ for pMOS) surrounded by a gate stack. The device is doped from source to drain with the same element type and concentration, such that there are no gradients or junctions. Fig. 1 presents a schematic view (A) and the longitudinal section (B) of an nMOS JNT. These devices are based on bulk conduction [4] and have shown to provide better subthreshold slope, DIBL and analog properties than inversion-mode devices of similar dimensions [5-6]. Recent papers have shown the temperature (7) influence on the behavior of JNTs [7-8]. The main characteristic was the absence of the zero temperature coefficient (ZTC) bias, i.e. a point in which the drain current is almost the same independently of the temperature. In these papers, this absence has been attributed to the higher threshold voltage (Vm) and the lower mobility (μ) dependences on T [7]. This paper shows that JNTs can present a ZTC bias, which strongly depends on the series resistance. © 2012 IEEE.
- Modeling the interface traps-related low frequency noise in triple-gate SOI junctionless nanowire transistors(2019) Trevisoli R.; Doria R.T.; Barraud S.; Pavanello M.A.© 2019 Elsevier B.V.The aim of this work is to propose a semi-analytical model for the low frequency noise caused by interface traps in Triple-Gate Junctionless Nanowire Transistors. The proposed model is based on a drain current model, which includes short channel effects influence. The surface potential and the occupied trap density equations are solved self consistently to obtain the traps influence in the static drain current, which is used to determine the trap-related noise. In this work, the low frequency noise of traps in discrete levels is analyzed. The model has been validated with 3D simulations considering different devices characteristics, biases and trap levels. Experimental results have also been used to demonstrate the model suitability.
- Substrate bias influence on the operation of junctionless nanowire transistors(2014) Trevisoli R.; Doria R.T.; De Souza M.; Pavanello M.A.The aim of this paper is to analyze the substrate bias influence on the operation of junctionless nanowire transistors based on 3-D simulated and experimental results, accomplished by modeled data. The threshold voltage, the maximum transconductance, the subthreshold slope, the drain-induced barrier lowering (DIBL), and the ION/IOFF ratio are the key parameters under analysis. It has been shown that the negative back bias can reduce the short-channel effects occurrence, improving the ION/ OFF ratio and DIBL. © 1963-2012 IEEE.
- Low temperature influence on performance and transport of Ω-gate p-type SiGe-on-insulator nanowire MOSFETs(2019) Paz B.C.; Casse M.; Barraud S.; Reimbold G.; Vinet M.; Faynot O.; Pavanello M.A.© 2019 Elsevier LtdThis work evaluates the operation of p-type Si0.7Ge0.3-On-Insulator (SGOI) nanowires from room temperature down to 5.2 K. Electrical characteristics are shown for long channel devices comparing narrow Ω-gate to quasi-planar MOSFETs (wide fin width). Analysis is performed starting from basic MOSFET electrical parameters extraction, evidence of quantum transport, transconductance and capacitance step-like behavior. Temperature and fin width influence over mobility results are discussed for uniaxial and biaxial compressive strained SGOI. Results are also compared to unstrained p-type SOI nanowires and effective mobility enhancement for SGOI nanowires is still observed for devices with fin width scaled down to 20 nm. Narrow SGOI NW presents mobility improvement over quasi-planar SGOI structure for all temperature range due to beneficial uniaxial strain over biaxial one. Cryogenic operation of nanowires allowed the dissociation of phonon and surface roughness mobility contributions, which are also discussed in this work. Similar phonon-limited mobility contribution dependence on temperature is obtained for both narrow SGOI and unstrained SOI transistors. In order to provide a complete study on the performance of SGOI nanowires, temperature influence is also investigated over analog parameters for narrow SGOI transistor.
- Methodology to separate channel conductions of two level vertically stacked SOI nanowire MOSFETs(2018) Paz B.C.; Casse M.; Barraud S.; Reimbold G.; Vinet M.; Faynot O.; Pavanello M.A.© 2018 Elsevier LtdThis work proposes a new method for dissociating both channel conductions of two levels vertically stacked inversion mode nanowires (NWs) composed by a Gate-All-Around (GAA) level on top of an Ω-gate level. The proposed methodology is based on experimental measurements of the total drain current (IDS) varying the back gate bias (VB), aiming the extraction of carriers’ mobility of each level separately. The methodology consists of three main steps and accounts for VB influence on mobility. The behavior of non-stacked Ω-gate NWs are also discussed varying VB through experimental measurements and tridimensional numerical simulations in order to sustain proposed expressions of mobility dependence on VB for the bottom level of the stacked structure. Lower mobility was obtained for GAA in comparison to Ω-gate. The procedure was validated for a wide range of VB and up to 150 °C. Similar temperature dependence of mobility was observed for both Ω-gate and GAA levels.
- Effect of the back bias on the analog performance of standard FD and UTBB transistors-based self-cascode structures(2017) Doria R.T.; Flandre D.; Trevisoli R.; De Souza M.; Pavanello M.A.© 2017 IOP Publishing Ltd.This work demonstrates that active back biasing can improve significantly the analog performance of two-transistors self-cascode structures. The study was performed by applying both standard and UTBB fully depleted (FD) SOI MOSFETs to the structures and has shown that a voltage gain improvement of about 7 dB is obtained when a forward back bias is applied to the drain-sided transistor of standard FD devices-based structure. In the case of UTBB transistors, an improvement larger than 5 dB of the output voltage gain is shown depending on the back bias applied to both n- or p-type devices. Finally, it is shown that the mirroring precision of current mirrors composed by SC structures can be more than 20% better than the one composed by single devices and the improvement is better when adequate back bias is applied.
- Junctionless nanowire transistors parameters extraction based on drain current measurements(2019) Trevisoli R.; Doria R.T.; de Souza M.; Barraud S.; Pavanello M.A.© 2019 Elsevier LtdThe aim of this work is to propose and qualify a systematic method for parameters extraction of Junctionless Nanowire Transistors (JNTs) based on drain current measurements and compact modeling. As junctionless devices present a different conduction mechanism than inversion-mode transistors, the methods developed for the latter devices either are not compatible or cannot be directly applied to JNTs before a deep analysis on their applicability. The current work analyzes the extraction of the series resistance, including a discussion about the influence of the first and second order mobility degradation factors, flatband voltage and low field mobility in junctionless transistors based only on static drain current curves. An analysis of the method accuracy considering the influence of the channel length, nanowire width and height, gate oxide thickness and doping concentration is also presented for devices with different characteristics through three-dimensional numerical simulations. The inclusion of the second order effects in a drain current model is also shown, considering the extracted values. The method applicability is also successfully demonstrated in experimental devices.
- Physical insights on the dynamic response of SOI n-and p-type junctionless nanowire transistors(2018) Doria R.T.; Trevisoli R.; de Souza M.; Pavanello M.A.© 2018, Brazilian Microelectronics Society. All rights reserved.— This work evaluates, for the first time, the roles of the intrinsic capacitances and the series resistance on the dynamic response of p-and n-type Junctionless Nanowire Transistors. The dynamic behavior evaluation will be carried out through the analysis of the limitation imposed by such parameters on the maximum oscillation frequency (fmax). In the sequence, it will be shown the impacts of fmax and the carriers’ transit time on the minimum switching time presented by JNTs. It has been observed that Junctionless devices present lower fmax than inversion mode transistors of similar dimensions due to higher resistance and lower transconductance. However, the intrinsic capacitances of such devices are smaller than the inversion mode ones, which compensates part of the degradation on fmax caused by the other parameters. Besides that, it is shown that transit time can be important on the dynamic behavior of long devices, but plays a negligible role in shorter ones.
- High temperature effects on harmonic distortion in submicron SOI graded-channel MOSFETs(2011) Emam M.; Pavanello M.A.; Danneville F.; Vanhoenacker-Janvier D.; Raskin J.-P.The effect of elevated temperature on the harmonic distortion in Graded-Channel MOSFETs is presented in this work. The Graded-Channel devices show interesting advantages in terms of nonlinear behavior compared to classical devices especially at higher temperatures up to 200°C. © (2011) Trans Tech Publications, Switzerland.
- Harmonic distortion analysis of triple gate SOI nanowire MOSFETS down to 100 K(2017) Paz B.C.; Doria R.T.; Casse M.; Barraud S.; Reimbold G.; Vinet M.; Faynot O.; Pavanello M.A.© 2017 Elsevier LtdThe linearity of triple gate nanowire transistors (NWs) implemented on a Silicon-On-Insulator (SOI) substrate is investigated in this work considering temperature (T) influence. The analysis is performed in long channel nanowire MOSFETs with different fin width (WFIN), from quasi-planar structures (WFIN = 10 μm) to narrow devices (9.5 nm), operating as single-transistor amplifiers from room temperature down to 100 K. The total, second and third order harmonic distortions (THD, HD2 and HD3, respectively) are extracted using the Integral Function Method (IFM). The analysis is divided in two parts. First, a fixed input signal is applied at the gate of the single-transistor amplifiers and, then, the output signal is fixed. Transport parameters such as effective mobility (μeff), mobility degradation coefficient (θ) and series resistance (RS) have been extracted down to 100 K and correlated to the distortion to explain linearity peaks behavior with temperature and fin width. Narrow transistors have shown improved linearity mainly due to higher intrinsic voltage gain (AV) considering the entire temperature range. Low temperature operation has shown to degrade the linearity characteristics of both wide and narrow NW MOSFETs.