Artigos
URI permanente para esta coleçãohttps://repositorio.fei.edu.br/handle/FEI/798
Navegar
3 resultados
Resultados da Pesquisa
Artigo 0 Citação(ões) na Scopus The roles of the gate bias, doping concentration, temperature and geometry on the harmonic distortion of junctionless nanowire transistors operating in the linear regime(2014-05-05) Rodrigo Doria; TREVISOLI, R.; Michelly De Souza; ESTRADA, M.; CERDEIRA, A.; Marcelo Antonio Pavanello© 2014, Journal of Integrated Circuits and Systems 2014. All rights received.The linearity of Junctionless nanowire transistors operating in the linear regime has been evaluated through experimental data and numerical simulations. The influences of the fin width, the gate bias, the temperature, the doping concentration and the geometry on the overall linearity have been evaluated. The increase of the series resistance associated both to the variation of the physical parameters and the incomplete ionization effect has shown to improve the second order distortion and degrade the third order one.- Analysis of the correlation between NBTI effect and the surface potential in junctionless nanowire transistors(2020-01-05) GRAZIANO JUNIOR, N.; TREVISOLI, R.; Rodrido Doria© 2020, Brazilian Microelectronics Society. All rights reserved.— This paper discusses the nature of degradation by NBTI effect in pMOS junctionless nanowire transistors when varying the density of interface traps. The data obtained in simulations are analyzed through the extracted hole density to-gether with the surface potential and it is demonstrated how the quality of gate oxide affects the performance of such transistors, when the density of traps, the channel width, the doping con-centration and the gate bias are varied.
- Effect of substrate bias and temperature variation in the capacitive coupling of soi utbb mosfets(2021-08-23) DA SILVA, E. M.; TREVISOLI, R.; Rodrido Doria© 2021, Brazilian Microelectronics Society. All rights reserved.In this work, the electrical features related to the capacitive coupling and temperature influence of the Ultra-Thin Body and Buried Oxide SOI MOSFET (UTBB) transistors are explored through numerical simulations calibrated to experimental data. The impact of the substrate bias is observed for a set of values ranging from-3 V to 2 V for a temperature range between 100 K and 400 K. Also, structures with n-and ptype ground planes (GP-P and GP-N) and without GP have been evaluated. This approach analyzes the capacitive coupling through the body factor and shows that the negative biasing for all GP types significantly improves the structure coupling and that the device with P-type ground plane has the lowest value of body factor for all the evaluated conditions. The dependence of the body factor on the temperature has shown to be negligible for longer devices. However, for devices shorter than 50 nm, the position of the maximum electrons concentration inside the silicon layer may affect the capacitive coupling.