Artigos
URI permanente para esta coleçãohttps://repositorio.fei.edu.br/handle/FEI/798
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7 resultados
Resultados da Pesquisa
- Influence of fin width and channel length on the performance of buffers implemented with standard and strained triple-gate nFinFETs(2009-09-03) Marcelo Antonio Pavanello; MARTINO, J. A.; SIMOEN, E.; ROOYACKERS, R.; COLLAERT, N.; CLAEYS, C.In this work the application of standard and strained triple-gate FinFETs in unity-gain source-follower configuration is compared. The analysis is performed by evaluating the buffer voltage gain with respect to the fin width and channel length as well as the total harmonic distortion. It is demonstrated that the application of strained material in narrow FinFETs, when the devices are operating in double-gate mode, can be beneficial for the performance of buffers in any channel length. On the other hand, for triple-gate FinFETs or quasi-planar ones the degradation of the output conductance overcomes the transconductance improvements from strained material and the performance of standard buffers is better than of strained ones. Narrow strained buffers also offer better harmonic distortion. © The Electrochemical Society.
- Three-dimensional simulation of biaxially strained triple-gate FinFETs: A method to compute the fin width and channel length dependences on device electrical characteristics(2010-01-05) Rodrigo Doria; Marcelo Antonio PavanelloStrained devices have been the focus of recent research works due to the boost in the carrier mobility providing a drain current enhancement. Consequently, simulating strained transistors become of major importance in order to predict their characteristics. However, the non-uniformity of the stress distribution creates a dependence of the strain on the device dimensions. This dependence cannot be easily considered in a TCAD simulation. This work shows that the definition of an analytical function for the strain components can overcome this drawback in the stress simulation. Maximum transconductance gain was used as the key parameter to compare simulated and experimental data. The results obtained show mat the simulations with the analytical function agree wim the measurements. ©The Electrochemical Society.
- X-ray radiation effects in the circular-gate transistors(2011-01-05) CIRNE, K. H.; Marcilei Aparecida Guazzelli; DE LIMA, J. A.; SEIXAS JUNIOR, L. E.; Salvador GimenezThis work performs two experimental comparative analyses of the x-ray radiation effects in the Conventional, Wave and Overlapping-Circular-Gate nMOSFETs. In the first experiment, the x-ray radiation influence is studied without biasing the devices during the irradiation process, considering two channel lengths and after they have been exposed up to a x-ray irradiation of 1.5 Grad and with a dose ratio of 22 Mrad/min. The second one performs an experimental comparative study of the x-ray radiation influence between the Conventional and Overlapping-Circular Gate nMOSFET for a channel length equal to 12 μm, when they are submitted to the x-ray irradiation of 60 Mrad and maintaining the same bias conditions (overdrive gate and drain voltages) during the irradiation process. In both studies, we observe that the Overlapping-Circular Gate layout style presents higher x-ray irradiation robustness than those found in the other transistors studied, due to the absence of the bird's beak in Overlapping-Circular Gate MOSFET. ©The Electrochemical Society.
- An analytical model for the non-linearity of triple gate SOI MOSFETs(2011-01-05) Rodrigo Doria; MARTINO, J. A.; SIMOEN, E.; CLAEYS, C.; Marcelo Antonio PavanelloThis work proposes a physically-based analytical model for the non-linearity of Triple-Gate MOSFETs. The model describes the second order harmonic distortion (HD2), usually the major non-linearity source, as a function of the device dimensions, the series resistance, the low field mobility and the mobility degradation factor (θ). The model was applied to transistors of different channel lengths and fin widths and allowed to conclude that θ is the parameter which most contributes for the increase of HD2. The model was validated for both unstrained and strained FinFETs. ©The Electrochemical Society.
- Comparison between SOI nMOSFET's under uniaxial and biaxial mechanical stress in analog applications(2011-09-02) DE SOUZA, M. A. S.; SOUZA, F. N.; Michelly De Souza; Marcelo Antonio PavanelloThis work presents a study comparing the analog performance of uniaxially and biaxially strained planar Silicon-on-Insulator nMOSFETs for a wide range of channel lengths. The study is performed via two-dimensional numerical and process simulation and supported by experimental measurements. The comparison between devices from the same technology with these two strained techniques demonstrated that higher intrinsic voltage gain is obtained for biaxial mechanical stress. However, the transconductance is higher for uniaxial mechanical stress for shorter devices (below 550 nm) leading to larger unity gain frequency. On the other hand, despite both strain techniques degrades the output conductance, this degradation with channel length shortening is less pronounced for devices under biaxial mechanical stress. © The Electrochemical Society.
- Comparative study of biaxial and uniaxial mechanical stress influence on the low frequency noise of fully depleted SOI nMOSFETs operating in triode and saturation regime(2012-09-02) DE SOUZA, M. A. S.; Rodrido Doria; Michelly De Souza; MARTINO, J. A.; Marcelo Antonio PavanelloThis paper presents an experimental comparative study of uniaxial and biaxial strain techniques influence on the low frequency noise of planar fully depleted SOI nMOSFETs operating in linear and saturation regimes. The comparison between devices from the same technology with these two strained techniques demonstrated a reduction of low frequency noise for devices with both strain technologies in linear regime for shorter devices (below 410 nm). In saturation regime the reduction of low frequency noise for uniaxial and biaxial strain also occurs, but does not depend on the channel length, and the reduction of low frequency noise in favor of both strain technologies is more pronounced for channel length of 160 nm. © The Electrochemical Society.
- Analog behavior of submicron graded-Channel SOI MOSFETs varying the channel length, doping concentration and temperature(2013-05-16) NEMER, J. P.; Michelly De Souza; FLANDRE, D.; Marcelo Antonio PavanelloIn this paper the analog performance of Graded-Channel (GC) SOI nMOSFETs with deep submicrometer channel length is presented. Experimental data of GC transistors fabricated in an industrial 150 nm fully-depleted SOI technology from OKI Semiconductors were used to adjust the two-dimensional numerical simulations, in order to analyze the devices analog behavior by extrapolating their physical parameters. The obtained results show that the larger intrinsic voltage gain improvement occurs when the length of the lightly doped region is approximately 100 nm regardless the total channel length, doping concentration and temperature. © The Electrochemical Society.