Artigos
URI permanente para esta coleçãohttps://repositorio.fei.edu.br/handle/FEI/798
Navegar
8 resultados
Resultados da Pesquisa
- Modeling Quantum Confinement in Multi-Gate Transistors with Effective Potential(2022) SOARES, C. S.; BAIKADI, P. K. R.; ROSSETO, A. C. J.; Marcelo Antonio Pavanello; VASILESKA, D.; WIRTH, G. I.© 2022 IEEE.Particle-based Monte Carlo device simulators are an efficient tool to investigate the performance and reliability of transistors. The semiclassical theoretical model employed in the Monte Carlo device simulator is unsuccessful to describe some aspects of the multi-gate transistors that come from the quantum behavior of charge carriers. To take into consideration the space-quantization effects in these simulators, a quantum correction is necessary. We propose to include an effective potential in the Monte Carlo device simulator to address the wave-like behavior of electrons in n-type silicon FinFET and n-type silicon nanowire transistors. The effective potential has a unique parameter, which can be adjusted to find a line density using an Effective Potential-Poisson solver that matches with the line density calculated using a Schrodinger-Poisson solver. We demonstrated that using the effective potential model, the effect of the electron confinement is well described.
- Simulation of miller OpAmp analog circuit with FinFET transistors(2012-03-17) CONTRERAS, E.; CERDEIRA, A.; Marcelo Antonio PavanelloIn this paper we present a methodology to use the Symmetric Doped Double-Gate Model implemented in Verilog-A to simulate analog circuits with FinFET Technology. A Miller operational Amplifier was simulated in SPICE simulator and the results were validated comparing them with experimental data published in previous works. © 2012 IEEE.
- OCTO FinFET(2013-09-06) NETO E, D.; SIMOEN, E.; CLAEYS, C.; GIMENEZ, S. OCTO FinFET. Chip in Curitiba 2013 - SBMicro 2013: 28th Symposium on Microelectronics Technology and Devices.; SIMOEN, E.; CLAEYS, C.; Salvador GimenezThis paper is conceptual and introduces for the first time a new concept of structural design for FinFETs, the OCTO FinFET, which consists of an evolution of the Diamond layout style. Three-dimensional numerical simulations were performed in order to compare the performance between this new architecture and the conventional counterpart. It is shown that this layout style can significantly improve important parameters such as drain current, transconductance and on-state resistance. © 2013 IEEE.
- An accurate closed-expression model for FinFETs parasitic resistance(2015) Pereira A.S.N.; Giacomini R.© 2015 Elsevier Ltd. All rights reserved.A new closed-expression analytic model for parasitic resistance of FinFETs (Fin-Field-Effect-Transistors), which allows a fast estimation of this parasitic element, is proposed and evaluated in this work. The parasitic resistance is one of the most significant parameter for performance and reliability degradations in scaled devices. The model is based in the current distribution observed in three-dimensional simulations and is very accurate when compared to experimental data. The contact resistance was modeled using a variable impedance transmission line model, to approximate source and drain geometries to the real shapes of these regions. The model has a closed expression, without adjustment parameters. All results were compared with two previous models presented in literature, and the proposed model was the one which presented the best accuracy: percent errors below 10% for different source and drain doping concentrations, contact lengths, extension lengths, contact resistivity and fin widths.
- Low-frequency noise of n-type triple gate FinFETs fabricated on standard and 45 rotated substrates(2013) Doria R.T.; Martino J.A.; Simoen E.; Claeys C.; Pavanello M.A.This paper studies the impact of the 45 substrate rotation on the low-frequency noise (LFN) of triple gate nFinFETs. The overall LFN has been extracted for both standard and 45 substrate rotated devices of several fin widths at different drain and gate voltage biases focusing on their operation in saturation regime. A general view of the mechanisms which govern the low-frequency noise in MOS devices is provided and a brief discussion on the physical origins of the LFN in the evaluated devices is carried out. It has been noted that the LFN in non-rotated (0 rotated) and 45 rotated devices operating in the linear regime shows 1/f behavior independent on the gate bias, whereas in the saturation regime both 1/f and Lorentzian (1/f2) noises are observed. The former one prevails at lower frequencies and the 1/f2 noise at higher ones. In this case, the corner frequency shows an exponential dependence on the gate bias. © 2013 Elsevier Ltd. All rights reserved.
- Analog performance of standard and strained triple-gate silicon-on-insulator nFinFETs(2008) Pavanello M.A.; Martino J.A.; Simoen E.; Rooyackers R.; Collaert N.; Claeys C.This work shows a comparison between the analog performance of standard and strained Si n-type triple-gate FinFETs with high-κ dielectrics and TiN gate material. Different channel lengths and fin widths are studied. It is demonstrated that both standard and strained FinFETs with short channel length and narrow fins have similar analog properties, whereas the increase of the channel length degrades the early voltage of the strained devices, consequently decreasing the device intrinsic voltage gain with respect to standard ones. Narrow strained FinFETs with long channel show a degradation of the Early voltage if compared to standard ones suggesting that strained devices are more subjected to the channel length modulation effect. © 2008 Elsevier Ltd. All rights reserved.
- Harmonic distortion of 2-MOS structures for MOSFET-C filters implemented with n-type unstrained and strained FINFETS(2011) Doria R.T.; Simoen E.; Claeys C.; Martino J.A.; Pavanello M.A.This work investigates the harmonic distortion (HD) in 2-MOS balanced structures composed of triple gate FinFETs. HD has been evaluated through the determination of the third-order harmonic distortion (HD3), since this represents the major non-linearity source in balanced structures. The 2-MOS structures with devices of different channel lengths (L) and fin widths (W fin) have been studied operating in the linear region as tunable resistors. The analysis was performed as a function of the gate voltage, aiming to verify the correlation between operation bias and HD3. The physical origins of the non-linearities have been investigated and are pointed out. Being a resistive circuit, the 2-MOS structure is generally projected for a targeted on-resistance, which has also been evaluated in terms of HD3. The impact of the application of biaxial strain has been studied for FinFETs of different dimensions. It has been noted that HD3 reduces with the increase of the gate bias for all the devices and this reduction is more pronounced both in narrower and in longer devices. Also, the presence of strain slightly diminishes the non-linearity at a similar bias. However, a drawback associated with the use of strain engineering consists in a significant reduction of the on-resistance with respect to unstrained devices. © 2011 Elsevier Ltd. All rights reserved.
- Evaluation of triple-gate FinFETs with SiO2-HfO2-TiN gate stack under analog operation(2007) Marcelo Antonio Pavanello; MARTINO, J. A.; SIMOEN, E.; ROOYACKERS, R.; COLLAERT, N.; CLAEYS, C.This work presents the analog performance of nMOS triple-gate FinFETs with high-κ dielectrics, TiN gate material and undoped body from DC measurements. Different fin widths and devices with and without halo implantation are explored. No halo FinFETs can achieve extremely large gain and improved unity gain frequency at similar channel length than halo counterparts. The FinFETs with 110 nm long channel achieve an intrinsic gain of 25 dB. Extremely large Early voltages have been measured on long channel nMOS with no halo and relatively wide fins compared to the results usually reported in the literature. The large Early voltage obtained suggests that the devices operate in the onset of volume inversion due to the low doping level of the device body. © 2007 Elsevier Ltd. All rights reserved.