Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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3 resultados
Resultados da Pesquisa
- Technological parameters scaling influence on the analog performance of Graded-Channel SOI nMOSFET transistors(2014-01-20) ASSALTI, R.; Marcelo Antonio Pavanello; Michelly DE Souza; FLANDRE, D.This paper aims at analyzing, through two-dimensional numerical simulations and experimental results, the influence of technological parameters downscaling on the analog performance of Graded-Channel FD SOI nMOSFET transistors. Front gate oxide and silicon film thicknesses, channel doping concentration, total channel and lightly doped region lengths have been varied to target the highest intrinsic voltage gain.
- Dependence of the optimum length of light doped region of GC SOI nMOSFET with front gate bias(2014-10-29) ASSALTI, R.; Marcelo Antonio Pavanello; FLANDRE, D.; Michelly De SouzaThis work assesses the analog performance of Graded-Channel FD SOI nMOSFET transistors regarding the dependence of gate voltage overdrive over the length of lightly doped region which maximizes the intrinsic voltage gain, unit gain frequency and breakdown voltage. It is shown that the optimum length of lightly doped region depends on the target application of GC devices.
- Asymmetric Self-Cascode versus Graded-Channel SOI nMOSFETs for analog applications(2015-10-13) ASSALTI, R.; Marcelo Antonio Pavanello; FLANDRE, D.; Michelly De SouzaThis paper compares the performance of Asymmetric Self-Cascode and Graded-Channel SOI nMOSFETs, both proposed to improve the analog performance of fully depleted SOI nMOSFETs. The differences at device level are evaluated and the impact of their application in basic analog circuits, i.e. common-source amplifier, source-follower and common-source current mirror are explored through experimental results.