Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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8 resultados
Resultados da Pesquisa
- Impact of series resistance on the drain current variability in inversion mode and junctionless nanowire transistors(2023-10-05) SILVA, L. M. B. DA; Marcelo Antonio Pavanello; CASSÉ, M.; BARRAUD, S.; VINET, M.; FAYNOT, O.; Michelly De Souza© 2023 Elsevier LtdThis work analyzes the influence of source-drain series resistance variability over the drain current in junctionless and inversion mode nanowire transistors. A comparison between drain current and Y-function variability is presented using experimental data of nanowires with different widths and channel lengths. The source-drain series resistance variability is also presented. The results indicates that source-drain series resistance influence is higher on drain current variability for junctionless than inversion mode nanowire transistors.
- High Temperature and Width Influence on the GIDL of Nanowire and Nanosheet SOI nMOSFETs(2023-01-05) Michelly De Souza; CERDEIRA, A.; ESTRADA, M.; BARRAUD, S.; CASSE, M.; VINET, M.; FAYNOT, O.; Pavanello M. A.AuthorIn this work, an experimental evaluation of Gate-Induce Drain Leakage (GIDL) current is presented for nanowire and nanosheet-based SOI transistors. The effects of fin width and temperature increase are studied. Obtained results indicate that the increase in device width makes the GIDL current more sensitive to temperature increase. Three-dimensional numerical simulations have shown that despite the reverse junction leakage increase with temperature, leakage current in nanosheet and nanowire transistors is composed predominantly of GIDL current. The change in valence and conduction bands caused by temperature increase favors the band-to-band tunneling, which is responsible for the worsening of GIDL at high temperatures.
- An Experimental Evaluation of Fin Width and Low-Temperature Influence on GIDL in Stacked SOI Nanowires(2022) Michelly De Souza; RODRIGUES, J. C.; MARINIELLO, G.; CASSE, M.; BARRAUD, S.; VINET, M.; FAYNOT, O.; Marcelo Antonio Pavanello© 2022 IEEE.In this work, an experimental evaluation of the gate-induced drain leakage (GIDL) of vertically stacked SOI nanowire (NW) FETs is carried out, as a function of temperature for the first time. It is shown that at room temperature, NW width decrease improves gate coupling favoring longitudinal band-to-band-tunneling, which increases normalized GIDL current. The increase of GIDL current with fin narrowing becomes more pronounced with temperature reduction. The influence of fin width has been evaluated, showing that GIDL variation with temperature depends on the device geometry.
- New method for individual electrical characterization of stacked SOI nanowire MOSFETs(2017-10-18) PAZ, B.C.; CASSE, M.; BARRAUD, S.; REIMBOLD, G.; VINET, M.; FAYNOT, O.; Marcelo Antonio PavanelloA new systematic procedure to separate the electrical characteristics of advanced stacked nanowires (NWs) with emphasis on mobility extraction is presented. The proposed method is based on I-V measurements varying the back gate bias (VB) and consists of three basic main steps, accounting for VB influence on transport parameters. Lower mobility was obtained for the top GAA NW in comparison to bottom Q-NW. Temperature dependence of carrier mobility is also studied through the proposed method up to 150°C.
- Cryogenic operation of Ω-gate p-type SiGe-on-insulator nanowire MOSFETs(2018-03-19) PAZ, B. C.; Marcelo Antonio Pavanello; CASSE, M.; BARRAUD, S.; REIMBOLD, G.; VINET, M.; FAYNOT, O.This work evaluates the operation of p-type Si0.7Ge0.3-on-insulator (SGOI) nanowires from room temperature down to 5.2K. Electrical characteristics are shown for long channel devices comparing narrow Ω-gate to quasi-planar MOSFETs (wide fin width). Results show oscillations in both transconductance and gate to channel capacitance curves for temperatures smaller than 50K and fin width of 20nm due to quantum confinement effects. Improvement on the effective mobility for SGOI in comparison to SOI nanowires is still observed for devices with fin width scaled down to 20nm. Similar phonon-limited mobility contribution dependence on temperature is obtained for both narrow SGOI and SOI nanowires.
- Back bias impact on effective mobility of p-type nanowire SOI MOSFETs(2018-08-27) PAZ, B .C.; CASSE, M.; BARRAUD, S.; REIMBOLD, G.; VINET, M.; FAYNOT, O.; Marcelo Antonio PavanelloIn this work we investigated the impact of back bias on the effective mobility of p-type Ω-gate nanowire SOI MOSFETs. Evaluation is performed through both measurements and 3D numerical simulations. Electrostatic potential, electric field and holes density are studied through simulations to explain transconductance degradation with back bias increase. Holes mobility linear dependence on back bias is found to be related to the inversion channel density and its position along the silicon thickness. Besides, this work also sheds light on the dependence of the drain current in vertically stacked NW with back bias, as its behavior is determined by the bottom Ω-gate level.
- Influence of Fin Width Variation on the Electrical Characteristics of n-Type Junctionless Nanowire Transistors at High Temperatures(2020-09-05) RIBEIRO, T. A.; BARRAUD, S.; BERGAMASCHI, F. E.; Marcelo Antonio PavanelloThis work studied the effects of the fin width variation on Silicon-on-Insulator Junctionless Nanowire Transistors (JNTs) working in the temperature range of 300K to 500K. The effects of the temperature on the measured drain current, and gate capacitance, and on the extracted electrical parameters such as the threshold voltage, the subthreshold slope and the electron mobility were analyzed. Results show that JNTs with larger fin width may present better carrier mobility at a higher temperature than narrow ones as the degradation due to phonon scattering is decreased and the impurity scattering becomes more relevant. It is demonstrated that JNTs with narrow fin width show higher phonon scattering and higher mobility variation with the temperature than wider ones.
- Influence of fin width variation on the electrical characteristics of n-type junctionless nanowire transistors at high temperatures(2021-11-21) RIBEIRO, T. A.; BERGAMASCHI, F.E.; BARRAUD, S.; Marcelo Antonio PavanelloThis work studied the effects of the fin width variation on Silicon-on-Insulator Junctionless Nanowire Transistors (JNTs) working in the temperature range of 300 K to 500 K. The effects of the temperature on the measured drain current and gate capacitance, and on the extracted electrical parameters such as the threshold voltage, the subthreshold slope, and the electron mobility were analyzed. Results show that JNTs with larger fin width may present better carrier mobility at a higher temperature than narrow ones as the degradation due to phonon scattering is decreased and the impurity scattering becomes more relevant. It is demonstrated that JNTs with narrow fin width show higher phonon scattering and higher mobility variation with the temperature than wider ones.