Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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6 resultados
Resultados da Pesquisa
- Analysis of Fin Width Influence on the Carrier's Mobility of Nanowire MOSFETs(2021-08-31) CCOTO, C. U. C.; BERGAMASHI, F. E.; Marcelo Antonio Pavanello©2021 IEEE.In this work, the study of the effective electron mobility (peff) of n-channel MOS transistor nanowires is presented. By extracting the mobility of the top and sidewall using the surface current separation technique together with the split-CV method. Analyzing the comparison of simulated TCAD results and experimental transistors fabricated with various fin widths (12nm-82nm) and how the effect of varying the fin width and applied substrate voltages interfere with carrier mobility values.
- Extraction of the Back Channel Mobility in SOI Nanowire MOS Transistors under Substrate Biasing(2022-07-04) BERGAMASHI, F. E.; WIRTH, G. I.; BARRAUD, S.; CASSE, M.; VINET, M.; FAYNOT, O.; Marcelo Antonio Pavanello© 2022 IEEE.In this work, an analysis of the effective mobility of SOI nanowire MOS transistors is performed by separating the mobility of electrons in the back channel, which is created when substrate bias is applied. Measurements are done in n-type devices with an Ω-gate structure and variable channel length. Both longer and shorter channel devices present higher mobility in the back channel, but strong mobility reduction is observed with the increase of the substrate bias, reaching values close to that of the front channel at strong back bias levels. This effect is independent of the applied gate voltage overdrive. Three-dimensional TCAD simulation validates the method used to separate the back channel mobility, showing that the front channel mobility is not changed by the increase in substrate bias.
- TCAD Evaluation of the Active Substrate Bias Effect on the Charge Transport of Ω-Gate Nanowire MOS Transistors with Ultra-Thin BOX(2022-01-05) BERGAMASHI, F. E.; Marcelo Antonio PavanelloAuthorThis work presents an analysis of the application of active substrate bias (or back bias) on the charge transport properties of n-type Ω-gate SOI nanowire MOS transistors with thin buried oxide (BOX) and variable fin width. Additionally, the influence of back bias on the electrical parameters of these devices is also investigated through DC parameters such as on-to-off-state current ratio and DIBL. The evaluation is conducted by 3D TCAD simulations calibrated with experimental data. The application of negative back bias on nMOS transistors not only shifts the threshold voltage, but also causes mobility degradation due to the negative potential on the channel pushing the charges against the gate oxide interface. On the other hand, when positive back bias is applied, despite the mobility improvement allowed by the back channel’s superior mobility and the front channel’s less compacted inversion layer, at higher substrate bias levels, a strong mobility degradation is observed in the back channel due to the substrate’s high electric field, resulting in reduction of the channel’s overall effective mobility. The application of positive substrate bias degrades the subthreshold slope, leading to smaller on-to-off-state current ratio, as well as the reduced control of channel charges by the gate electrode worsens the DIBL.
- Self-heating-based analysis of gate structures on junctionless nanowire transistors(2017-08-28) BERGAMASHI, F. E.; Marcelo Antonio Pavanello; Mariniello, G.In this paper, an analysis on the thermal profile of Junctionless Nanowire Transistors is made, where self-heating effects are evaluated in devices with a large 4-contact gate, comparing the results with a minimized gate structure device. Tests are performed for different fin widths and fin heights. The analysis is based on three-dimensional simulations. Results showed that the gate structure is impactful to the thermal behavior of narrow small transistors, but not wide and tall ones.
- Experimental analysis of self-heating effects using the pulsed IV method in junctionless nanowire transistors(2018-08-27) BERGAMASHI, F. E.; MARINIELLO, G.; BARRAUD, S.; Marcelo Antonio PavanelloThis paper discusses the occurrence of self-heating in Junctionless Nanowire Transistors, observed through drain current degradation in the transient regime. The analysis is made by performing experimental measurements using the Pulsed IV method in transistors with varied dimensions. It is shown that the junctionless nanowire's susceptibility to self-heating is not high enough to significantly affect the transistor's characteristics, where for all cases current degradation lower than 4.5% is seen.
- Impact of substrate bias on the mobility of n-type-gate SOI nanowire MOSFETs(2019-08-05) BERGAMASHI, F. E.; BARRAUD, S.; CASSE, M.; VINET, M.; FAYNOT, O.; PAZ, B. C.; Marcelo Antonio PavanelloThis work presents the impact of substrate bias on the mobility of high-κ gate n-type Ω-gate SOI nanowire MOS transistors. The analysis is performed through experimental measurements and tridimensional numerical simulations. Mobility and its degradation coefficients are extracted using the Y-function method. The results showed that back bias increase has a beneficial effect on mobility for negative voltages and up to 10V, due to reduction in surface roughness scattering. But for higher back bias levels, mobility starts undergoing severe degradation. Simulations show that strong positive back bias drags the inversion layer down to the second interface, where mobility is shown to be lower.