Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
Navegar
5 resultados
Resultados da Pesquisa
- High Temperature and Width Influence on the GIDL of Nanowire and Nanosheet SOI nMOSFETs(2023-01-05) Michelly De Souza; CERDEIRA, A.; ESTRADA, M.; BARRAUD, S.; CASSE, M.; VINET, M.; FAYNOT, O.; Pavanello M. A.AuthorIn this work, an experimental evaluation of Gate-Induce Drain Leakage (GIDL) current is presented for nanowire and nanosheet-based SOI transistors. The effects of fin width and temperature increase are studied. Obtained results indicate that the increase in device width makes the GIDL current more sensitive to temperature increase. Three-dimensional numerical simulations have shown that despite the reverse junction leakage increase with temperature, leakage current in nanosheet and nanowire transistors is composed predominantly of GIDL current. The change in valence and conduction bands caused by temperature increase favors the band-to-band tunneling, which is responsible for the worsening of GIDL at high temperatures.
- Analysis of the Gate-Induced Drain Leakage of SOI Nanowire and Nanosheet MOS Transistors at High Temperatures(2022-07-04) Michelly De Souza; CERDEIRA, A.; ESTRADA, M.; BARRAUD, S.; CASSE, M.; VINET, M.; FAYNOT, O.; Marcelo Antonio Pavanello© 2022 IEEE.This work presents a comparison between the Gate-Induced Drain Leakage (GIDL) current of the nanowire (tri-gate MOSFET with narrow fin width) and nanosheet (tri-gate MOSFET with wide fin width) SOI MOSFETs at high temperatures, in the range between 300 K and 580 K. The study is conducted using experimental data, corroborated with 3D TCAD simulations. It is demonstrated that the GIDL current normalized by the total fin width is larger in nanosheet MOSFET than for the nanowire at high temperatures. Additionally, the nanosheet device presents a larger variation of the normalized GIDL current with the temperature than the nanowire one.
- On the compact modelling of Si nanowire and Si nanosheet MOSFETs(2022) CERDEIRA, A.; ESTRADA, M.; Marcelo Antonio PavanelloIn this paper, three-dimensional technology computer aided design simulations are used to show that the electron concentration, current density, and electric field distribution from the interface at the lateral channels and from the top channel to the centre of the silicon wire, in nanowire and nanosheet structures, are practically same. This characteristic makes it possible to consider that the total channel width for these structures is equal to the perimeter of the transistor sheet, allowing to extend of the application of the symmetric doped double-gate model (SDDGM) model to nanowires and nanosheets metal-oxide-semiconductor field effect transistors, with no need to include new parameters. The model SDDGM is validated for this application using several measured and simulated structures of nanowires and nanosheets transistors, with different aspect ratios of fin width and fin height, showing very good agreement between measured or simulated characteristics and modelled. SDDGM is encoded in Verilog-A language and implemented in the SmartSPICE circuit simulator.
- Simulation of OTA's with double-gate graded-channel MOSFETS using the symmetric doped double-gate model(2010-01-05) CENTRERAS, E.; CERDEIRA, A.; Marcelo Antonio PavanelloIn this paper Operational Transconductance Amplifiers (OTA's) were simulated in SPICE, using the Symmetric Doped Double-Gate Model which includes the capacitances of Double-Gate (DG) transistors. In this work, all the transistors have been simulated using just one model for lightly doped transistor (TLD) and high doped transistor (THd) N-channel devices and P-channel devices. These OTA's show an improvement in the high open-loop voltage gain which is related mainly to the reduction of the drain output conductance which give higher Early voltages for DG GC transistors. ©The Electrochemical Society.
- Adaption of triple gate junctionless MOSFETs analytical compact model for accurate circuit design in a wide temperature range(2018-03-19) CERDEIRA, A.; AVILA-HERRERA, F.; ESTRADA, M.; DORIA, R. T.; Marcelo Antonio PavanelloThis paper presents the necessary adaptions on the proposed compact analytical model of triple gate junctionless nanowire transistors for accurate description of device electrical characteristics in a wide temperature range. The model validation is performed by comparison against experimental results showing very good agreement, with continuous current and its derivatives in all regions of operation and temperatures.