Repositório do Conhecimento Institucional do Centro Universitário FEI
 

Engenharia Elétrica

URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21

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2017 - 20183

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Autor: search.filters.author.Marcelo Antonio PavanelloPeriódico: search.filters.ispartof.2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017

Resultados da Pesquisa

Agora exibindo 1 - 3 de 3
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    Artigo de evento 3 Citação(ões) na Scopus
    Experimental comparative analysis between junctionless and inversion mode nanowire transistors down to 10 nm-long channel lengths
    (2018-10-18) Rodrigo Doria; TREVISOLI, R.; Michelly De Souza; Marcelo Antonio Pavanello; VINET, M.; CASSE, M.; FAYNOT, O.
    This paper aims at presenting, for the first time, an experimental comparative analysis between the main electrical parameters of Junctionless (JNT) and inversion mode nanowire (IM) transistors fabricated in SOI technology down to channel length of 10 nm. The analysis has shown that JNTs present larger immunity to SCEs with respect to IM nanowires of similar dimensions. However, JNTs have shown poorer Ion than IM devices, which could be compensated through the application of multifin JNTs, at cost of increasing area consumption.
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    Artigo de evento 4 Citação(ões) na Scopus
    New method for individual electrical characterization of stacked SOI nanowire MOSFETs
    (2017-10-18) PAZ, B.C.; CASSE, M.; BARRAUD, S.; REIMBOLD, G.; VINET, M.; FAYNOT, O.; Marcelo Antonio Pavanello
    A new systematic procedure to separate the electrical characteristics of advanced stacked nanowires (NWs) with emphasis on mobility extraction is presented. The proposed method is based on I-V measurements varying the back gate bias (VB) and consists of three basic main steps, accounting for VB influence on transport parameters. Lower mobility was obtained for the top GAA NW in comparison to bottom Q-NW. Temperature dependence of carrier mobility is also studied through the proposed method up to 150°C.
  • N/D
    Artigo de evento 7 Citação(ões) na Scopus
    Lateral spacers influence on the effective channel length of junctionless nanowire transistors
    (2017-10-16) TREVISOLI, R.; Rodrido Doria; Michelly De Souza; Marcelo Antonio Pavanello
    This work presents a deep analysis on the effect of lateral spacers on the performance of the Junctionless Nanowire Transistors. An analytical model to account for the spacer influence on the device electrical behavior is proposed and validated through numerical simulation results.