Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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5 resultados
Resultados da Pesquisa
- Experimental Demonstration of Ω-Gate SOI Nanowire MOS Transistors' Mobility Variation Induced by Substrate Bias(2022) BERMAMASCHI, F. E.; RIBEIRO, T. A.; PAZ, B. C.; Michelly De Souza; BARRAUD, S.; CASSE, M.; VINET, M.; FAYNOT, O.; Marcelo Antonio Pavanello© 1963-2012 IEEE.This work investigates the carrier mobility variation in Ω-gate silicon-on-insulator (SOI) nanowire MOS transistors induced by substrate (or back) biasing. The analysis is carried out through experimental measurements and 3-D TCAD simulation, performed in n-type devices with variable fin width. Mobility enhancement is observed for lower back bias levels, due to the initial conduction through the Si-BOX interface, which presents higher mobility, prior to the activation of the front channel. As back bias is increased, however, the strong substrate-induced electric field in the back channel (BC) is responsible for worsening scattering mechanisms in the BC, such as surface roughness and acoustic phonon scattering, inducing mobility degradation. The effect is amplified as the fin width increases. For short-channel devices, the use of back bias was more beneficial for mobility due to a stronger mobility enhancement and lower mobility degradation.
- Variability Modeling in Triple-Gate Junctionless Nanowire Transistors(2022-01-05) TREVISOLI, R.; Marcelo Antonio Pavanello; Rodrigo Doria; CAPOVILLA, C.E.; BARRAUD, S.; Michelly De SouzaIEEEThis work aims at proposing an analytical model for the variability of the threshold voltage and drain current in junctionless nanowire transistors. The model is continuous in all operation regions and has been validated through Monte Carlo simulations using a physically based drain current model and 3-D numerical simulations. A discussion about the influences of each variability source based on the proposed model is carried out. Finally, the modeled results are compared to the experimental data for a fully physical validation.
- Surface-potential-based drain current analytical model for triple-gate junctionless nanowire transistors(2012-01-05) TREVISOLI, R. D.; Rodrido Doria; Michelly De Souza; DAS, S.; FERAIN, I.; Marcelo Antonio PavanelloThis paper proposes a drain current model for triple-gate n-type junctionless nanowire transistors. The model is based on the solution of the Poisson equation. First, the 2-D Poisson equation is used to obtain the effective surface potential for long-channel devices, which is used to calculate the charge density along the channel and the drain current. The solution of the 3-D Laplace equation is added to the 2-D model in order to account for the short-channel effects. The proposed model is validated using 3-D TCAD simulations where the drain current and its derivatives, the potential, and the charge density have been compared, showing a good agreement for all parameters. Experimental data of short-channel devices down to 30 nm at different temperatures have been also used to validate the model. © 2012 IEEE.
- A New Method for Series Resistance Extraction of Nanometer MOSFETs(2017-07-05) TREVISOLI, R.; Rodrido Doria; Michelly De Souza; BARRAUD, S.; VINET, M.; CASSE, M.; REIMBOLD, G.; FAYNOT, O.; GHIBAUDO, G.; Marcelo Antonio PavanelloThis paper presents a new method for the series resistance extraction in ultimate MOSFETs using a single drain current versus gate voltage characteristic curve. The method is based on the Y-function curve, such that the series resistance is obtained through the curve of the total resistance as a function of the inverse of the Y-function. It includes both first-and second-order mobility degradation factors. To validate the proposed method, numerical simulations have been performed for devices of different characteristics. Besides, the method applicability has been demonstrated for experimental silicon nanowires and FinFETs. Apart from that, devices with different channel lengths can be used to estimate the mobility degradation factor influence.
- Analytical Model for Low-Frequency Noise in Junctionless Nanowire Transistors(2020-24-24) TREVISOLI, RENAN; Marcelo Antonio Pavanello; CAPOVILLA, CARLOS EDUARDO; BARRAUD, SYLVAIN; DORIA, RODRIGO TREVISOLIThis article aims at proposing a compact analytical model for the low-frequency noise (LFN) of junctionless nanowire transistors (JNTs), operating at different bias conditions and temperatures. The model is validated through tridimensional numerical simulations, accounting for different trap configurations, as well as devices with different channel lengths, nanowire widths, and doping concentrations. Experimental results of short-channel junctionless transistors have also been used to demonstrate the model's applicability and accuracy.