Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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24 resultados
Resultados da Pesquisa
- Low temperature influence on performance and transport of Ω-gate p-type SiGe-on-insulator nanowire MOSFETs(2019) Paz B.C.; Casse M.; Barraud S.; Reimbold G.; Vinet M.; Faynot O.; Pavanello M.A.© 2019 Elsevier LtdThis work evaluates the operation of p-type Si0.7Ge0.3-On-Insulator (SGOI) nanowires from room temperature down to 5.2 K. Electrical characteristics are shown for long channel devices comparing narrow Ω-gate to quasi-planar MOSFETs (wide fin width). Analysis is performed starting from basic MOSFET electrical parameters extraction, evidence of quantum transport, transconductance and capacitance step-like behavior. Temperature and fin width influence over mobility results are discussed for uniaxial and biaxial compressive strained SGOI. Results are also compared to unstrained p-type SOI nanowires and effective mobility enhancement for SGOI nanowires is still observed for devices with fin width scaled down to 20 nm. Narrow SGOI NW presents mobility improvement over quasi-planar SGOI structure for all temperature range due to beneficial uniaxial strain over biaxial one. Cryogenic operation of nanowires allowed the dissociation of phonon and surface roughness mobility contributions, which are also discussed in this work. Similar phonon-limited mobility contribution dependence on temperature is obtained for both narrow SGOI and unstrained SOI transistors. In order to provide a complete study on the performance of SGOI nanowires, temperature influence is also investigated over analog parameters for narrow SGOI transistor.
- Methodology to separate channel conductions of two level vertically stacked SOI nanowire MOSFETs(2018) Paz B.C.; Casse M.; Barraud S.; Reimbold G.; Vinet M.; Faynot O.; Pavanello M.A.© 2018 Elsevier LtdThis work proposes a new method for dissociating both channel conductions of two levels vertically stacked inversion mode nanowires (NWs) composed by a Gate-All-Around (GAA) level on top of an Ω-gate level. The proposed methodology is based on experimental measurements of the total drain current (IDS) varying the back gate bias (VB), aiming the extraction of carriers’ mobility of each level separately. The methodology consists of three main steps and accounts for VB influence on mobility. The behavior of non-stacked Ω-gate NWs are also discussed varying VB through experimental measurements and tridimensional numerical simulations in order to sustain proposed expressions of mobility dependence on VB for the bottom level of the stacked structure. Lower mobility was obtained for GAA in comparison to Ω-gate. The procedure was validated for a wide range of VB and up to 150 °C. Similar temperature dependence of mobility was observed for both Ω-gate and GAA levels.
- Junctionless nanowire transistors parameters extraction based on drain current measurements(2019) Trevisoli R.; Doria R.T.; de Souza M.; Barraud S.; Pavanello M.A.© 2019 Elsevier LtdThe aim of this work is to propose and qualify a systematic method for parameters extraction of Junctionless Nanowire Transistors (JNTs) based on drain current measurements and compact modeling. As junctionless devices present a different conduction mechanism than inversion-mode transistors, the methods developed for the latter devices either are not compatible or cannot be directly applied to JNTs before a deep analysis on their applicability. The current work analyzes the extraction of the series resistance, including a discussion about the influence of the first and second order mobility degradation factors, flatband voltage and low field mobility in junctionless transistors based only on static drain current curves. An analysis of the method accuracy considering the influence of the channel length, nanowire width and height, gate oxide thickness and doping concentration is also presented for devices with different characteristics through three-dimensional numerical simulations. The inclusion of the second order effects in a drain current model is also shown, considering the extracted values. The method applicability is also successfully demonstrated in experimental devices.
- Compact modeling of triple gate junctionless MOSFETs for accurate circuit design in a wide temperature range(2019) Pavanello M.A.; Cerdeira A.; Doria R.T.; Ribeiro T.A.; Avila-Herrera F.; Estrada M.© 2019 Elsevier LtdThis paper presents the extension of proposed physically-based continuous compact analytical model of triple gate junctionless nanowire transistors for accurate description of device electrical characteristics in a wide temperature range from room temperature up to 500 K. The model validation is performed by comparison against tridimensional numerical simulation and experimental data showing very good agreement, with continuous description of drain current and its derivatives in all regions of operation and temperatures.
- Study of silicon n- and p-FET SOI nanowires concerning analog performance down to 100 K(2017) Paz B.C.; Casse M.; Barraud S.; Reimbold G.; Vinet M.; Faynot O.; Pavanello M.A.© 2016 Elsevier LtdThis work presents an analysis of the performance of silicon triple gate SOI nanowires aiming the investigation of analog parameters for both long and short channel n-type and p-MOSFETs. Several nanowires with fin width as narrow as 9.5 nm up to quasi-planar MOSFETs 10 μm-wide are analyzed. The fin width influence on the analog parameters is studied for n-type and p-MOSFETs with channel lengths of 10 μm and 40 nm, at room temperature. The temperature influence is analyzed on the analog performance down to 100 K for long channel n-MOSFETs by comparing the quasi-planar device to the nanowire with fin width of 14.5 nm. The intrinsic voltage gain, transconductance and output conductance are the most important figures of merit in this work. An explicit correlation between these figures of merit and the mobility behavior with temperature is demonstrated.
- Charge-based compact analytical model for triple-gate junctionless nanowire transistors(2016) Avila-Herrera F.; Paz B.C.; Cerdeira A.; Estrada M.; Pavanello M.A.© 2016 Elsevier Ltd.A new compact analytical model for short channel triple gate junctionless transistors is proposed. Based on a previous model for double-gate transistors which neglected the fin height effects, a new 3-D continuous model has been developed, including the dependence of the fin height and the short channel effects. An expression for threshold voltage is presented. The model defines a one-dimensional semiconductor effective capacitance due to the width and the height of the fin, which in turn redefines the potentials and charges, without altering the general modeling procedure. Threshold voltage roll-off, subthreshold slope, DIBL and channel length modulation, as well as, the mobility degradation and the velocity saturation have been introduced into the model. The validation was done by 3-D numerical simulations for different fin heights and channel lengths, as well as, by experimental measurements in nanowire transistors with doping concentrations of 5 × 1018 and 1 × 1019 cm-3. The developed model is suitable for describing the current-voltage characteristics in all operating regions from double-gate to nanowire transistor with only 8 adjusting parameters.
- Compact model for short-channel symmetric double-gate junctionless transistors(2015) Avila-Herrera F.; Cerdeira A.; Paz B.C.; Estrada M.; Iniguez B.; Pavanello M.A.© 2015 Elsevier Ltd.Abstract In this work a compact analytical model for short-channel double-gate junctionless transistor is presented, considering variable mobility and the main short-channel effects as threshold voltage roll-off, series resistance, drain saturation voltage, channel shortening and saturation velocity. The threshold voltage shift and subthreshold slope variation is determined through the minimum value of the potential in the channel. Only eight model parameters are used. The model is physically-based, considers the total charge in the Si layer and the operating conditions in both depletion and accumulation. Model is validated by 2D simulations in ATLAS for channel lengths from 25 nm to 500 nm and for doping concentrations of 5 × 1018 and 1 × 1019 cm-3, as well as for Si layer thickness of 10 and 15 nm, in order to guarantee normally-off operation of the transistors. The model provides an accurate continuous description of the transistor behavior in all operating regions.
- Low-frequency noise of n-type triple gate FinFETs fabricated on standard and 45 rotated substrates(2013) Doria R.T.; Martino J.A.; Simoen E.; Claeys C.; Pavanello M.A.This paper studies the impact of the 45 substrate rotation on the low-frequency noise (LFN) of triple gate nFinFETs. The overall LFN has been extracted for both standard and 45 substrate rotated devices of several fin widths at different drain and gate voltage biases focusing on their operation in saturation regime. A general view of the mechanisms which govern the low-frequency noise in MOS devices is provided and a brief discussion on the physical origins of the LFN in the evaluated devices is carried out. It has been noted that the LFN in non-rotated (0 rotated) and 45 rotated devices operating in the linear regime shows 1/f behavior independent on the gate bias, whereas in the saturation regime both 1/f and Lorentzian (1/f2) noises are observed. The former one prevails at lower frequencies and the 1/f2 noise at higher ones. In this case, the corner frequency shows an exponential dependence on the gate bias. © 2013 Elsevier Ltd. All rights reserved.
- Compact core model for Symmetric Double-Gate Junctionless Transistors(2014) Cerdeira A.; Avila F.; Iniguez B.; De Souza M.; Pavanello M.A.; Estrada M.A new charge-based compact analytical model for Symmetric Double-Gate Junctionless Transistors is presented. The model is physically-based and considers both the depletion and accumulation operating conditions including the series resistance effects. Most model parameters are related to physical magnitudes and the extraction procedure for each of them is well established. The model provides an accurate continuous description of the transistor behavior in all operating conditions. Among important advantages with respect to previous models are the inclusion of the effect of the series resistance and the fulfilment of being symmetrical with respect to drain voltage equal to zero. It is validated with simulations for doping concentrations of 5 × 10 18 and 1 × 1019 cm-3, as well as for layer thickness of 10 and 15 nm, allowing normally-off operation. © 2014 Elsevier B.V.
- On the improvement of DC analog characteristics of FD SOI transistors by using asymmetric self-cascode configuration(2016) De Souza M.; Flandre D.; Doria R.T.; Trevisoli R.; Pavanello M.A.© 2015 Elsevier Ltd. All rights reserved.This paper demonstrates the improvement of DC analog performance of FD SOI transistors provided by the adoption of asymmetric self-cascode (A-SC) configuration. It consists of two transistors connected in series with gates shortened, acting as a single device. The doping concentration of the two transistors in the structure is different, leading to higher threshold voltage of the transistor at the source side of the composite structure than that of the transistor at the drain side. By reducing the doping concentration level at the channel of the transistor at drain side of the composite structure, forcing it to work in saturation, part of the applied drain bias is absorbed and does not reach the transistor close to the source, which is the main responsible for the overall device characteristics. As a result, larger drain current level and transconductance are obtained in comparison to symmetric self-cascode (where both transistors present same doping level) apart from promoting output conductance reduction. The transconductance, output conductance, Early voltage, and intrinsic voltage gain are used as figures of merit to demonstrate and validate the advantages of the proposed structure. The influence of channel length and doping concentration are also evaluated. The A-SC configuration is fully compatible with any standard FD SOI MOSFET technology with multiple threshold voltages. A simulation analysis demonstrates the feasibility of the proposed asymmetric structure in a UTBB FD SOI technology.
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