Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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3 resultados
Resultados da Pesquisa
- Use of back gate bias to enhance the analog performance of planar FD and UTBB SOI transistors-based self-cascode structures(2015-10-13) Rodrido Doria; FLANDRE, D.; TREVISOLLI, R.; Michelly De Souza; Marcelo Antonio PavanelloThis paper reports, for the first time, the use of back gate bias to improve the intrinsic voltage gain of self-cascode structures composed by planar FD and UTBB SOI MOSFETs. It is shown a voltage gain improvement larger than 10 dB when either a forward back bias is applied to the drain-side transistor or a reverse back bias is applied to the source side device.
- Effect of channel doping concentration on the harmonic distortion of asymmetric n-and p-type self-cascode MOSFETs(2015-09-04) D´OLIVEIRA, L. M.; Rodrido Doria; Marcelo Antonio Pavanello; FLANDRE. D.; Michelly De Souza© 2015 IEEE.This paper compares the harmonic distortion of n-and p-type symmetric (S-SC) and asymmetric self-cascode (A-SC) structures of different channel doping concentrations, providing a physic analysis of its behavior. This study is made by experimental measurements of structures composed by n-and p-type MOSFETs taking the second and third order harmonics as figures of merit. For strong inversion, the normalized second order harmonic distortion was better for the A-SC structures composed by devices with lower channel doping concentration on the transistor near the drain for either n-and p-type composite MOSFETs.
- Effective channel length in Junctionless Nanowire Transistors(2015-10-13) TREVISOLLI, R.; Rodrido Doria; Michelly De Souza; Marcelo Antonio PavanelloThe aim of this work is to analyze the influence of the lateral depletion induced by the gate towards the source/drain regions on the effective channel length of Junctionless Nanowire Transistors. The effective channel length increase at the subthreshold regime is analyzed by means of simulations together with experimental results, showing that the JNT can be significantly longer than the gate length.